2.1 Setting the IP address of the NIC
2.2 Enabling Jumbo Frame of the NIC
2.3 Disabling Flow Control and Interrupt Moderation.
2.4 Setting Number of RSS Queues and RSS Base Processor Number
3 Test Result Using FPGA and PC
4.3 Send and Receive Data Test (Half Duplex Test)
1 Overview
This document illustrates an example of running the UDP100G-IP demo using two different test environments to transfer UDP data. The first test environment employs a single FPGA board to transfer UDP data with a PC that runs a test application for transferring UDP data over 100G Ethernet. The performance result may be constrained by the resources of the PC. On the other hand, the best performance for transferring UDP data using UDP100G-IP can be achieved by utilizing two FPGA boards in the second test environment, where they transfer data to each other.
The document covers three topics, which include setting up the 100G Ethernet connection on the PC to achieve optimal performance for transferring data via 100G Ethernet in section 2. In section 3, the console example and test results are presented when operating under the first test environment, involving FPGA and PC. Lastly, section 4 shows the console example when operating the second test environment, involving FPGA and FPGA. Each topic is described in further detail as follows.
2 PC Setup
Before running demo, please check the network setting on your PC. The example for setting 100G Ethernet connection is described as follows.
2.1 Setting the IP address of the NIC
To set the IP address of the NIC, follow the steps below.
Figure 1 Setting IP Address of the NIC on PC
1) Open Local Area Connection Properties of the 100G Ethernet connection, as shown in the left window of Figure 1.
2) Select “TCP/IPv4” and click on Properties.
3) Set the IP address = 192.168.100.25 and the Subnet mask = 255.255.255.0, as illustrated in the right window of Figure 1.
2.2 Enabling Jumbo Frame of the NIC
Figure 2 Jumbo Frame Setting
1) On Local Area Connection Properties window, click on “Configure”, as shown in the left windows of Figure 2.
2) On Advanced Tab, select “Jumbo Packet” and set Value to “9014 Bytes” for Jumbo Frame support, as shown in the right windows of Figure 2. Setting value to “1514 Bytes” (for non-Jumbo Frame transfer) may reduce performance.
2.3 Disabling Flow Control and Interrupt Moderation
Figure 3 Flow Control and Interrupt Moderation Disabled
1) Select “Flow Control” and set the value to “Disabled”, as shown in the left window of Figure 3.
2) Select “Interrupt Moderation” and set the value to “Disabled”, as shown in the right window of Figure 3.
2.4 Setting Number of RSS Queues and RSS Base Processor Number
Figure 4 Number of RSS Queues and RSS Base Processor Number Setting
1) Set the Maximum Number of RSS Queues to a value greater than 4. For example, set to 8 Queues.
2) If the Ethernet card has multiple Ethernet port, ensure that the RSS Base Processor Number of each port does not overlap. For example, if there are two Ethernet ports and both are set with a maximum of 8 RSS queues, the RSS Base Processor Number should be set to 0 for the first port and 8 for the second port.
3) Click the “OK” button to save all settings and close the configuration windows.
2.5 Power Option Setting
Figure 5 Power Options
1) Open Control Panel and select Power Options, as shown in the left window of Figure 5.
2) Change setting to High Performance, as shown in the right window of Figure 5.
2.6 Firewall Setting
Figure 6 Firewall Configuration
1) Open the Control Panel and select Windows Firewall.
2) Click “Turn Windows Firewall on or off”.
3) Under both Private and Public network settings, select “Turn off Windows Firewall”.
4) Click “OK” button to confirm and apply the setting.
3 Test Result Using FPGA and PC
3.1 Display UDPIP Parameters
Choose option ‘0’ to display the UDP/IP parameters. The console will show either seven parameters in Client/Server mode or eight parameters in Fixed-MAC mode.
Figure 7 Display Current Parameter Result
Here are the details of the parameters.
2) FPGA MAC address: This parameter sets the 48-bit hex value to be the MAC address of the FPGA. The default value is 0x000102030405.
3) FPGA IP: This parameter sets the IP address of FPGA. The default value is 192.168.100.42.
Note: This value is used as a Server IP address parameter for the test application on PC.
4) FPGA port number: This parameter sets the port number of the FPGA. The default value is 4000.
Note: This value is used as a Server port parameter for the test application on PC.
5) Target MAC address (displayed when running Fixed-MAC mode only): This parameter sets the 48-bit hex value as the MAC address of the target device. If the UDP100G-IP and the PC are on the same network, this is the MAC address of the target device. If they are in different networks, this is the MAC address of the gateway. The default value is 0x554433221100.
6) Target IP: This parameter sets the IP address of the target device (100G Ethernet on PC). The default value is 192.168.100.25.
7) Target port number (Target->FPGA): This parameter sets the port number of the target device to receive UDP payload data. The default value is 61000.
8) Target port number (FPGA->Target): This parameter sets the port number of the target device to send UDP payload data. The default value is 60000
To change any of these parameters, the user can set them by using the menu option [1] (Reset UDPIP parameter).
3.2 Reset UDPIP parameters
Choose option ‘1’ from the menu to reset the IP and modify IP parameters. This menu allows the user to change IP settings or reset the UDP100G-IP. Upon selection of this option, the current parameters are displayed on the console. Press ‘x’ to keep the same parameters, or press any other key to modify them. Once the parameters are confirmed, the UDP100G-IP is reset and the initialization process begins.
This menu contains seven or eight parameters that must be set. Each parameter is validated before being loaded into the UDP100G-IP. If the input is invalid, the parameter remains unchanged. Once all parameters have been loaded, the IP is reset. The details of each parameter are described in section 3.1 (Display UDPIP Parameter), and their valid ranges are provided below.
Figure 8 Change IP Parameter Result
1) Mode: Input ‘0’ to initialize the IP as Client mode.
Note: When the PC and FPGA are connected to different networks, which cannot communicate via the ARP process, the UDP100G-IP must be run in Fixed-MAC mode to manually set the target MAC address via the console.
2) FPGA MAC address: Input 12 digits of hex value, prefixed by “0x” to input it as a hex value.
3) FPGA IP address: Input four decimal digits separated by “.”, where the valid range for each digit is 0-255.
4) FPGA port number: The valid range is 0-65535.
5) Target MAC address (displayed only when running Fixed-MAC mode): Input 12 digits of hex value, prefixed by “0x” to input it as a hex value.
6) Target IP address: Similar to FPGA IP address, this value is a set of four decimal digits.
7) Target port number (Target->FPGA): The valid range is 0-65535.
8)
Target port number (FPGA->Target): The
valid range is 0-65535
After setting the parameters, the final values are displayed on the console. Then, the reset signal is sent to the IP, and it initializes using the new parameters. Finally, “IP initialization complete” is displayed on the console once the initialization process is completed, as shown in Figure 8.
3.3 Send Data Test
Choose option ‘2’ from the menu to send data from an FPGA to a PC. The test application, “udpdatatest.exe”, is called on the PC with specified parameters via Command prompt for receiving data. Simultaneously, the user inputs the test parameters for sending data on the FPGA console. The steps to run the test are outlined below.
Figure 9 Send Data Test Using Jumbo Frame with Data Verification Disabled
1) On the FPGA console, input two parameters to initiate the Send data test.
· Transfer size: The transfer size is specified in bytes. The valid range is 64 - 0xFFFF_FFFF_FFC0. The input must be aligned to 64. If inputting a decimal number, enter the digits. For hexadecimal values, prefix the input with “0x”.
· Packet size: The packet size is specified in bytes. The valid range is 64 – 8960. The input must be aligned to 64. Similar to the transfer size, decimal values can be entered directly, while hexadecimal values must be prefixed with “0x”.
Note: If packet size exceeds 1472 bytes, the packet output from UDP100G-IP will be a jumbo frame. In this case, the PC must support jumbo frame.
2) If all inputs are valid, the recommended parameters to run test application on the PC will be displayed. The FPGA consoled will then display “Press any key to start data sending …”, indicating it is waiting for the application to be run on the PC.
3) On the Command prompt, input the test parameters following the recommended values, except for the last two parameters, which can be adjusted for performance testing. The “udpdatatest” application in Send mode requires five parameters and two optional parameters.
>> udpdatatest [Dir] [FPGAIP] [FPGAPort] [PCPort] [ByteLen] <Pattern> <Timeout>
· Dir : Set to ‘r’ to receive test data from the FPGA.
· FPGAIP : Set to the same value as the FPGA IP address.
· FPGAPort : Set to the same value as the FPGA port number.
· PCPort : Set to the same value as the target port number (FPGA->Target).
·
ByteLen : Input the same
value as “Input transfer size” of step 1).
Optional parameters
· Pattern : ‘1’- enable data verification, ‘0’-disable data verification.
The default value is ‘1’ if no input is provided.
· Timeout : Timeout in msec unit. Valid values range from 50 to 65536.
It is recommended to set it to 100 for 100G Ethernet speed.
The default value is 100 if no input is provided.
4) After running the test application on the Command Prompt of the PC, a summary of parameter settings is displayed, and the application waits for received data from the FPGA.
5) On the FPGA console, user enters any key(s) to start sending data. While data is being transferred, the current size of the transferred data is displayed on both the FPGA console (transmit data size) and the Command Prompt (receive data size) every second.
6) Once all data has been sent, “Send data complete” is displayed on the FPGA console. On the PC, the test application completes under one of two conditions: first, when the total number of received data equals the set value (no data loss), and second, when no new data is received until a timeout occurs. If a timeout occurs, an error message is displayed on the Command Prompt. If the test application enables data verification, the position of the first error is also displayed. Finally, the total number of transferred data and the performance are displayed on the FPGA console (transmit performance) and the Command Prompt (receive performance).
Figure 9 shows an example of the Send data test using high-performance settings, which include transmitting packets with jumbo frame size and disabling data verification in the test application. The left window displays the FPGA console, while the right window displays the Command prompt on the PC. Due to PC resource limitations, the performance is constrained, and packet loss occurs during transmission.
When data verification is enabled, the processing load on the PC increases, which results in a higher data loss rate, as illustrated in Figure 10.
Figure 10 Send Data Test Using Jumbo Frame with Data Verification Enabled
In contrast, when using a small transfer size, the PC may receive data without any loss. However, in such cases, the transfer completes too quickly for the application to measure performance meaningfully, as demonstrated in Figure 11.
Figure 11 Send Data Test without Data Loss
If the input is invalid, an error message: “Out-of-range input” or “Invalid input” will be displayed. After that, the operation is cancelled, as shown in Figure 12 - Figure 13.
Figure 12 Error from Invalid Transfer Size
Figure 13 Error from Invalid Packet Size
3.4 Receive Data Test
Choose option ‘3’ from the menu to receive data sent from a PC to an FPGA. The test application, “udpdatatest.exe”, is executed on the PC with specified parameters via Command prompt for sending data. Simultaneously, the user inputs the test parameters for receiving and verifying data on the FPGA console. The steps to run the test are outlined below.
1) On the FPGA console, input two parameters to initiate the Receive data test.
· Transfer size: The transfer size is specified in bytes. The valid range is 64 - 0xFFFF_FFFF_FFC0. The input must be aligned to 64. If inputting a decimal number, enter the digits. For hexadecimal values, prefix the input with “0x”.
· Data verification mode: Set to ‘0’ to disable data verification or ‘1’ to enable data verification to verify data sent from the PC.
2) If all inputs are valid, the recommended parameters to run the test application on the PC will be displayed. The FPGA console will then display “Wait data from Target …”, indicating it is waiting for the application to be run on the PC.
3) On the Command prompt, input the test parameters following the recommended values, except for the last two parameters, which can be adjusted for performance testing. The “udpdatatest” application in Send mode requires five parameters and one optional parameter.
>> udpdatatest [Dir] [FPGAIP] [FPGAPort] [PCPort] [ByteLen] <Pattern>
· Dir : Set to ‘t’ to send test data to the FPGA.
· FPGAIP : Set to the same value as the FPGA IP address.
· FPGAPort : Set to the same value as the FPGA port number.
· PCPort : Set to the same value as the target port number (Target->FPGA).
· ByteLen : Input the same value as “Input transfer size” of step 1).
Optional parameters
· Pattern : ‘1’- Incremental pattern, ‘0’- dummy pattern.
The default value is ‘1’ if no input is provided.
4) After running the test application on the Command Prompt of the PC, a summary of parameter settings is displayed, and data transmission to the FPGA begins. While data is being transferred, the current size of the transferred data is displayed on both the FPGA console (receive data size) and the Command Prompt (transmit data size) every second.
5) Once all data has been received, “Receive data completed” is displayed on the FPGA console after the FPGA receives all data. However, the FPGA has implemented a timer to trigger a timeout condition to terminate the data reception process if no new data is received until the timeout is reached. Upon completion of the data transfer, the total number of transferred data and the performance are displayed on the FPGA console (receive performance) and the Command Prompt (transmit performance).
Figure 14 shows an example of Receive data test when the data verification mode is disabled on the FPGA console. The left window displays the test results on the FPGA console, while the right window displays the test results on the Command prompt).
Figure 15 shows and example of Receive data test when the data verification mode is enabled on the FPGA console. The PC sends incremental data to the FPGA, and the left window displays the test result on the FPGA console, while the right window displays the test results on the Command prompt. If the verification module fails, an error message is displayed, as illustrated in Figure 16.
Figure 14 Receive Data Test with Disabling Data Verification
Figure 15 Receive Data Test with Enabling Data Verification
Figure 16 Receive Data Test and Data Verification Failure
3.5 Full Duplex Test
1) On the FPGA console, the user must input four parameters to initiate the full duplex test.
· Transfer size: The transfer size is specified in bytes. The valid range is 64 - 0xFFFF_FFFF_FFC0. The input must be aligned to 64. If inputting a decimal number, enter the digits. For hexadecimal values, prefix the input with “0x”.
· Packet size: The packet size is specified in bytes. The valid range is 64 – 8960. The input must be aligned to 64. Similar to the transfer size, decimal values can be entered directly, while hexadecimal values must be prefixed with “0x”.
Note: If packet size exceeds 1472 bytes, the packet output from UDP100G-IP will be a jumbo frame. In this case, the PC must support Jumbo frame.
· Data verification mode: Set to ‘0’ to disable data verification or ‘1’ to enable data verification to verify data sent from the PC.
· Mode: Defines how data transfer is initiated. When running the test with a PC, data transfer is initiated by the PC. The user must set the mode to ‘1’ to run UDP100G-IP in Target mode, which starts transmission only after receiving data.
2) If all inputs are valid, the recommended parameters to run the test application for sending and receiving data on the PC will be displayed. The FPGA console will then display “Wait data from Initiator …”, indicating it is waiting for the application to be run on the PC.
3) Open two Command Prompts on the PC, and input the test parameters following the recommended values. Refer to step 3) of the preceding sections (section 3.3 for Receive mode and section 3.4 for Send mode) for details on the parameter.
4) During the transfer, the current transferred data size in both directions is displayed every second on both the FPGA console and Command prompt.
5) Upon completion of the data transfer, “Transfer data complete” is displayed on the FPGA console. Finally, the total number of transferred data and the performance in both transfer directions are displayed on both the FPGA console and the Command Prompt.
Figure 17 displays the transfer performance during full-duplex operation with data verification disabled. The left window shows the test result on the FPGA console, while the right window presents the results on the PC Command prompts. In the right window, the upper pane shows receive performance, and the lower pane shows transmit performance.
Similar to Send Data Test, data loss is detected on PC. In this scenario, the receive software haltห due to a timeout condition, where no new data is received within the specified timeout period. As a result, the application displays an error message indicating the total amount of lost data.
Figure 18 shows an example of a test result without data loss, which occurs when the transfer size is small.
Figure 17 Full Duplex Test with Data Loss Detected on PC
Figure 18 Full Duplex Test with No Data Loss
4 Test Result Using Two FPGAs
4.1 Display UDPIP Parameters
Figure 19 Display Current Parameter Result
Here are the details of the parameters.
1) Mode: This parameter sets the mode of the UDP100G-IP to initialize in Server, Client, or Fixed-MAC. Input ‘0’ for Client, ‘1’ for Server, or ‘2’ for Fixed-MAC.
2) FPGA MAC address: This parameter sets the 48-bit hex value as the MAC address of the FPGA. The default value is 0x000102030405 (Client mode/Fixed-MAC mode) or 0x001122334455 (Server mode).
3) FPGA IP: This parameter sets the IP address of the FPGA. The default value is 192.168.100.42 (Client mode/Fixed-MAC mode) or 192.168.100.25 (Server mode).
4) FPGA port number: This parameter sets the port number of the FPGA. The default value is 4000 (Client mode/Fixed-MAC mode) or 60000 (Server mode).
5) Target MAC address (displayed when running Fixed-MAC mode only): This parameter sets the 48-bit hex value as the MAC address of the target device. If the two FPGAs are on the same network, this is the MAC address of the target device. If they are in different networks, this is the MAC address of the gateway. The default value is 0x554433221100.
6) Target IP: This parameter sets the IP address of the target device. The default value is 192.168.100.25 (Client/Fixed-MAC mode) or 192.168.100.42 (Server mode).
7) Target port number (Target->FPGA): This parameter sets the port number of the target device to receive UDP payload data. The default value is 61000 for Client/Fixed-MAC mode or 4000 for Server mode.
8) Target port number (FPGA->Target): This parameter sets the port number of the target device to sending UDP payload data. The default value is 60000 for Client/Fixed-MAC mode or 4000 for Server mode
To change any of these parameters, the user can set them using the menu option [1] (Reset UDPIP parameters).
Note: Ensure that the FPGA and Target parameters of the two FPGA boards are cross-set. Specifically, the Target (remote) parameters of the first board must match the FPGA (local) parameters of the second board, and vice versa.
4.2 Reset UDPIP Parameters
Choose option ‘1’ from the menu to reset the IP and modify IP parameters. This menu allows the user to change the IP settings or reset the UDP100G-IP. Upon selection of this option, the current parameters are displayed on the console. Press ‘x’ to keep the same parameters, or press any other key to modify them. Once the parameters are confirmed, the UDP100G-IP is reset and the initialization process begins.
This menu contains seven or eight parameters that must be set. Each parameter is validated before being loaded into the UDP100G-IP. If the input is invalid, the parameter remains unchanged. Once all parameters have been loaded, the IP is reset. The details of each parameter are described in section 4.1 (Display UDPIP Parameter), and their valid ranges are provided below.
Note:
· Ensure that two FPGAs are configured in following initialization modes: Server <–> Client, Client <–> Fixed-MAC, or Fixed-MAC <-> Fixed-MAC.
· When operating in Server <-> Client mode, if the parameters on the Server need to be reset, the Client FPGA must also be reset. Additionally, the Server must be reset before the Client to ensure that it waits until the ARP request is sent by the Client.
· It is essential to match the parameters of both FPGAs as listed below.
· The Target IP address of board#1 = The FPGA IP address of board#2
· The FPGA IP address of board#1 = The Target IP address of board#2
Figure 20 Change IP Parameter Result
for Server/Client Mode
Figure 21 Change IP Parameter Result for Fixed-MAC Mode
1) Mode: Input ‘0’ (Client), ‘1’ (Server), ‘2’ (Fixed-MAC) to determine FPGA initialization mode.
2) FPGA MAC address: Input 12 digits of hex value, prefixed by “0x” to input it as a hex value.
3) FPGA IP address: Input four decimal digits separated by “.”, where the valid range for each digit is 0-255.
4) FPGA port number: The valid range is 0-65535.
5) Target MAC address (displayed only when running Fixed-MAC mode): Input 12 digits of hex value, prefixed by “0x” to input it as a hex value.
6) Target IP address: Similar to FPGA IP address, this value is a set of four decimal digits.
7) Target port number (Target -> FPGA): The valid range is 0-65535.
8) Target port number (FPGA -> Target): The valid range is 0-65535.
After setting the parameters, the final
values are displayed on the console. Then, the reset signal is sent to the IP, and
it initializes using the new parameters. Finally, “IP initialization complete” is
displayed on the console once the initialization process is complete, as shown in
Figure 20 and
Figure 21.
4.3 Send and Receive Data Test (Half Duplex Test)
Upon using two FPGA boards for data transfer in a single direction, choose option ‘2’ to initiate the send data test on the first board, and select option ‘3’ to initiate the receive data test on the other board. The user inputs the test parameters for each FPGA board by following the steps outlined below.
1) On the FPGA#1 console (Receive data test), input two parameters to initiate the Receive data test.
· Transfer size: The transfer size is specified in bytes. The valid range is 64 - 0xFFFF_FFFF_FFC0. The input must be aligned to 64. If inputting a decimal number, enter the digits. For hexadecimal values, prefix the input with “0x”.
· Data verification mode: Set to ‘0’ to disable data verification or ‘1’ to enable data verification to verify data sent from the FPGA#2.
2) If all inputs are valid, the FPGA#1 console will then display “Wait data from Target …”, indicating it is waiting for the data from the other FPGA. If any inputs are invalid, the console will display “Out-of-range input” or “Invalid input”, and the operation will be cancelled, similar to the test with PC (as shown in Figure 12 - Figure 13).
3) On the FPGA#2 console (Send data test), the user must input two parameters.
· Transfer size: The transfer size is specified in bytes. The valid range is 64 - 0xFFFF_FFFF_FFC0. The input must be aligned to 64. If inputting a decimal number, enter the digits. For hexadecimal values, prefix the input with “0x”. Input the same value as “Transfer size” from step 1).
· Packet size: The packet size is specified in bytes. The valid range is 64 – 8960. The input must be aligned to 64. Similar to the transfer size, decimal values can be entered directly, while hexadecimal values must be prefixed with “0x.
Note: If packet size exceeds 1472 bytes, the packet output from UDP100G-IP will be a jumbo frame. If two FPGA boards connect through other network devices, ensure that the network devices support jumbo frame.
4) Once all inputs are valid, the operation begins. “Press any key to start data sending ...” is displayed, awaiting the user’s input.
5) On the FPGA#2 console, the user inputs key(s) to start the data sending process. During data transmission, both FPGA consoles continuously display the current size of the transferred data every second.
6) Upon the completion of data transmission, “Send data complete” is displayed on the FPGA#2 console. Meanwhile, on the FPGA#1 console, “Receive data completed” appears once data reception concludes. Finally, both consoles display the total number of transferred data and the performance achieved.
Figure 22 and Figure 23 illustrate the results of half-duplex data transfer in an FPGA-FPGA environment utilizing jumbo frame and non-jumbo frame sizes, respectively. The performance achieved with jumbo frame size surpasses that of non-jumbo frame size by 7.9%. When employing FPGA-FPGA communication, a data transfer rate of 12,000 MB/sec is attained.
In case of invalid inputs, the console displays “Out-of-range input”, and the operation is subsequently cancelled, as illustrated in Figure 12 (similar to the FPGA <-> PC).
Figure 22 Send/Receive Data Test Using Jumbo Frame
Figure 23 Send/Receive Data Test Using Normal Frame
4.4 Full Duplex Test
Choose option ‘4’ to transfer data simultaneously in both directions using the same port number on both FPGAs. The user inputs the test parameters for FPGA board by following the steps outlined below.
1) On the FPGA#1 console, input three parameters to initiate the full duplex test.
· Transfer size: The transfer size is specified in bytes. The valid range is 64 - 0xFFFF_FFFF_FFC0. The input must be aligned 64. If inputting a decimal number, enter the digits. For hexadecimal values, prefix the input with “0x”.
· Packet size: The packet size is specified in bytes. The valid range is 64 – 8960. The input must be aligned 64. Similar to the transfer size, decimal values can be entered directly, while hexadecimal values must be prefixed with “0x”.
· Data verification mode: Set to ‘0’ to disable data verification or ‘1’ to enable data verification to verify data sent from the FPGA#2.
· Mode: Set to ‘1’ to enable Target mode, which initiates data transmission only after receiving data from FPGA#2.
2) If all input values are valid, the FPGA#1 console will display “Wait data from Initiator …”, indicating that the system is waiting for incoming data before initiating transmission.
3) On the FPGA#2 console, input four parameters, similar to step 1). However, the Mode must be set to Initiator, enabling data transmission after receiving user confirmation in step 4). Ensure that the values of the Transfer size and Data verification mode match the values set in step 1).
4) Once all inputs are valid, the FPGA#2 console will display “Ensure the device in Target mode has already run.” The user must press any key to start sending data.
5) During the transfer, the current size of transferred data in both directions is displayed on the FPGA consoles every second.
6) Upon completion, “Transfer data complete” is displayed on both FPGA consoles. The total amount of transferred data and the performance in both transfer directions are displayed on both FPGA consoles.
Figure 24 and Figure 25 illustrate the results of full-duplex data transfer in an FPGA-FPGA environment utilizing jumbo frames and non-jumbo frames, respectively. The performance results of full-duplex transfer match those of half-duplex transfer, as illustrated in the preceding section.
Figure 24 Full Duplex Test Using Jumbo Frame
Figure 25 Full Duplex Test Using Non-Jumbo
Frame
5 Revision History
|
Revision |
Date (D-M-Y) |
Description |
|
1.02 |
29-May-25 |
Add Mode input for Full-duplex test |
|
1.01 |
18-Aug-21 |
Update test performance using FPGA and PC |
|
1.00 |
5-Aug-21 |
Initial version release |