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1 Overview 2 Hardware 2.1 100G Ethernet (MAC) Subsystem (100GBASE-SR) 2.1.1 100G Ethernet Subsystem (UltraScale+) 2.1.2 100G Ethernet MAC Subsystem (Versal) 2.2 UDP100G-IP 2.3 CPU and Peripherals 2.3.1 AsyncAxiReg 2.3.2 UserReg 3 CPU Firmware (FPGA) 3.1 Display Parameters 3.2 Reset Parameters 3.3 Send Data Test 3.4 Receive Data Test 3.5 Full Duplex Test 3.6 Function List in CPU Firmware 4 Test Software (PC) 5 Revision History Return to Top

UDP100G-IP Reference Design Manual