Features Applications General Description Functional Description Control Block Parameter Registers (Param Regs) UDP/IP Engine Transmit Block Tx Data Buffer Tx Packet Buffer Packet Builder Receive Block Packet Filtering Rx Buffer Packet Splitter Rx Data Buffer User Block Ethernet MAC and PHY (10GBASE-R) DG 10GEMAC IP Low Latency Ethernet 10G MAC FPGA IP 10G BASE-R PHY IP Ethernet Hard IP Core I/O Signals Timing Diagram. IP Reset IP Initialization Data Transmission Data Reception Interrupt Ethernet MAC Interface Verification Methods Recommended Design Experience Ordering Information Revision History Return to Top