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1 Overview
2 Hardware
2.1 Ethernet MAC and PHY
2.1.1 DG 10GEMAC-IP
2.1.2 Low Latency Ethernet 10G MAC FPGA IP
2.1.3 Ethernet Hard IP on Agilex 7 or Agilex 5
2.2 UDP10G-IP
2.3 CPU and Peripherals
2.3.1 AsyncAvlReg
2.3.2 UserReg
3 CPU Firmware (FPGA)
3.1 Display Parameters
3.2 Reset Parameters
3.3 Send Data Test
3.4 Receive Data Test
3.5 Full Duplex Test
3.6 Function List in CPU Firmware
4 Test Software (PC)
5 Revision History
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UDP10G-IP Reference Design Manual