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1 Introduction
2 Hardware overview
2.1 10G/25G Ethernet PCS/PMA (10G BASE-R)
2.2 10G/25G Ethernet MAC
2.3 TenGMacIF (only applicable when using Xilinx EMAC IP)
2.4 UDP10G-IP
2.5 CPU and Peripherals
2.5.1 AsyncAxiReg
2.5.2 UserReg
3 CPU Firmware on FPGA
3.1 Display parameters
3.2 Reset IP
3.3 Send data test
3.4 Receive data test
3.5 Full duplex test
3.6 Function list in User application
4 Test Software (PC)
5 Revision History
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UDP10G-IP reference design manual