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Reference Designs & Application Notes	Vivado Project, See Reference design manual
Additional Items	Demo on KCU116/ZCU111/ FB2CGHH@KU15P card
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Features

· UDP/IP stack implementation

· Support IPv4 protocol

· Full-duplex transfer using different port numbers for Tx and Rx port

· Support multiple sessions by using multiple UDP25G IPs

· Support Jumbo frame

· Transmit packet size aligned to 128-bit, transmitted data bus size

· Total receive data size aligned to 128-bit, received data bus size

· Transmit/Receive buffer sizes, adjustable to balance resource usage and performance

· Simple data interface by standard FIFO interface at 128-bit data bus

· Simple control interface by 32-bit single-port RAM interface

· 64-bit AXI4 stream to interface for 10G/25G Ethernet MAC

· User clock frequency: EMAC Clock/2 – EMAC clock (195.3125 MHz – 390.625 MHz for 25GbE or 78.125 MHz – 156.25 MHz for 10GbE)

· Reference design available on KCU116, ZCU111, FB2CGHH@KU15P card

· Support IP fragmentation

· Customized service for following features

· Multicast IP

· Unaligned 128-bit data transferring

· Network parameter assignment by other methods

Table 1: Example Implementation Statistics for Ultrascale device

Family

Example Device

Fmax

(MHz)

CLB Regs

CLB LUTs

CLB¹

IOB

BRAMTile²

URAM

Design

Tools

Kintex UltraScale+

XCKU5P-FFVB676-2-E

350

2408

2314

475

Vivado2019.1

Zynq-Ultrascale+

XCZU28DR-FFVG1517-2-E

350

2408

2321

485

Vivado2019.1

Notes:

1) Actual logic resource dependent on percentage of unrelated logic

2) Block memory resources are based on 64kB Tx data buffer size, 16kB Tx packet buffer size, and 64kB Rx data buffer size.

Applications

Figure 1: UDP25G IP Application

The 25G Ethernet is a communication channel for transferring data with remote controlling system. When combined with the UDP/IP protocol, this system can transfer data in both Tx and Rx direction at high-speed rate via 25G Ethernet network. Additionally, UDP/IP supports data transfer for both one-by-one and broadcast systems. UDP25G IP is an integrated IP that enables data transfer via 25G Ethernet without requiring the use of CPU or external memory. It is suitable for applications that require high-speed data transfer for both Tx and Rx directions, such as video data streaming and real-time monitoring system using FPGA solutions.

Figure 1 shows an example application of video camera system, where video raw data from the camera is stored in a FIFO and forwarded to a remote system via 25G Ethernet using the UDP25G IP. The UDP25G IP supports full-duplex transfer simultaneously using different port numbers, allowing the Remote system to update the parameters for real-time controlling via 25G Ethernet while receiving the data from UDP25G IP via 25G Ethernet network.

General Description

Figure 2: UDP25G IP Block Diagram

The UDP25G IP core is a hardwired logic implementation of the UDP/IP stack that connects with the 10G/25G Ethernet MAC with PCS/PMA (BASE-R) module to form the lower layer hardware. The user interface of UDP25G IP consists of two interfaces, i.e., the Register interface for control signals and the FIFO interface for data signals.

The Register interface uses a 5-bit address for accessing up to 32 registers, including network parameters, command registers, and system parameters. Bi-directional data transfer is achieved using two sessions for each UDP25G IP, one session assigned for each direction. The network parameters for both sessions must be the same, except the port number on the target device. Network parameters must be set before de-asserting the reset signal to execute IP initialization. After finishing the reset operation and parameter initialization, the IP is ready to transfer data with the target device. Network parameters cannot be changed without a reset process. UDP25G IP has three initialization modes for obtaining the MAC address of the target device. Further details of each mode can be found in the IP Initialization topic.

To send UDP payload data, the user must set the total transfer size, packet size, and send command to the IP. The UDP payload data is transferred via TxFIFO interface which is 128-bit data size. There is no byte enable in the TxFIFO interface, so the transmitted data from the user must be aligned 128-bit. Additionally, the packet length and total amount of transmitted data must also be aligned to 128-bit.

On the other hand, when the UDP packet is received from the target, the UDP payload data is extracted and stored in the Rx data buffer. The user logic monitors FIFO status and detect the amount of received data and then asserts read enable to read the data via RxFIFO interface. The received data on the Rx FIFO I/F can be read when at least one 128-bit data is available in Rx data buffer. If total amount of received data is not aligned to 128-bit, the user cannot read the last data. The user must wait until the next data is received to fill the remaining byte of 128-bit data for reading the Rx data buffer.

To meet the user system requirements, which may be sensitive to the memory resources or the performance, the buffer size inside the IP can be assigned by the user. There are three buffers whose sizes can be adjusted, i.e., Tx data buffer, Tx packet buffer, and Rx data buffer. If the Tx buffer size is too small, the UDP25G IP may transmit all data to the target before the user fills the buffer with new data, causing the UDP25G IP to pause transmission and wait for new data from the user. On the other hand, if the Rx buffer size is too small, the buffer may become full if the user pauses reading data from the UDP25G IP for a long time, causing the UDP25G IP to reject the new received packet from the target.

UDP25G IP uses a 64-bit AXI4-Stream to connect with the Ethernet MAC. When Ethernet MAC is implemented by Xilinx IP core – 10G/25G Ethernet (MAC) Subsystem, the adapter logic (MacTxIF and MacRxIF) must be designed to act as the interface module between UDP25G IP and Ethernet MAC. However, DG 10G25GEMAC can connect to UDP25G IP directly without the adapter logic. More information about the hardware within the IP is described in the following section.

Functional Description

As shown in Figure 2, UDP25G IP core can be divided into three parts, i.e., control block, transmit block, and receive block. The details of each block are described as follows.

Control Block

· Reg

All parameters of the IP are set via register interface which has 5-bit address signals and 32-bit data signals. The timing diagram of the Register interface is similar to a single-port RAM interface, as shown in Figure 6. The write and read address are the same signal. Table 2 provides a description of each register.

Table 2: Register map Definition

RegAddr [4:0]	Reg Name	Dir	Bit	Description
00000b	RST	Wr /Rd	[0]	Reset IP. 0b: No reset, 1b: Reset. Default value is 1b. Once the network parameters have been assigned, the user can execute system initialization by setting this register to 1b and then 0b. This action loads the parameters into the IP. If the user needs to update certain parameters, this process must be repeated by setting this register to 1b and then 0b again. The RST register controls the following network parameters: SML, SMH, DML, DMH, DIP, SIP, DPN, SPN and SRV.
00001b	CMD	Wr	[0]	User command. Set 1b to start sending data. In order to start a new operation by setting this register, the system must first be in the Idle state. To confirm that the system is not busy, the user should read Busy signal or bit[0] of CMD register, which should be equal to 0b.
00001b	CMD	Rd	[0]	System busy flag. 0b: Idle, 1b: IP is busy during initialization or send command. This signal is also mapped as Busy (IP output signal).
00010b	SML	Wr /Rd	[31:0]	Define 32-bit lower MAC address (bit [31:0]) for this IP. To update this value, the IP must be reset by RST register.
00011b	SMH	Wr /Rd	[15:0]	Define 16-bit upper MAC address (bit [47:32]) for this IP. To update this value, the IP must be reset by RST register.
00100b	DIP	Wr /Rd	[31:0]	Define 32-bit target IP address. To update this value, the IP must be reset by RST register.
00101b	SIP	Wr /Rd	[31:0]	Define 32-bit IP address for this IP. To update this value, the IP must be reset by RST register.
00110b	DPN	Wr /Rd	[31:0]	[15:0]-Define 16-bit target port number using for the UDP25G IP to send data. [31:16]-Define 16-bit target port number using for the UDP25G IP to receive data. To update this value, the IP must be reset by RST register.
00111b	SPN	Wr /Rd	[15:0]	Define 16-bit port number for this IP. To update this value, the IP must be reset by RST register.

RegAddr [4:0]	Reg Name	Dir	Bit	Description
01000b	TDL	Wr	[31:0]	Define 32 lower bits (bit[31:0]) of 48-bit total Tx data length in byte unit. The value must be aligned to 16-byte because bit[3:0] are not used. Valid range is 16-0xFFFF_FFFF_FFF0. The 16 upper bits (bit[47:32]) are assigned in TDH register (01101b). The user must first set this register before setting CMD register=1b. When the IP executes the command and asserts Busy to 1b, the system will read this register, allowing the user to subsequently set the TDL/TDH register for the next command. If the same TDL/TDH is used in the subsequent command, the user is not required to set TDL/TDH again.
01000b	TDL	Rd	[31:0]	32 lower bits of 48-bit remaining transfer length in byte unit which does not transmit.
01001b	TMO	Wr	[31:0]	Define timeout value for awaiting the return of an ARP reply packet after sending an ARP request packet. The counter runs based on the Clk signal provided by the user, with the timer unit being equal to 1/Clk. If the ARP reply packet is not received in the specified time, IntOut will be asserted to 1b. It is recommended that the TMO is set to a value greater than 0x6000 or more than 100 msec timeout.
01001b	TMO	Rd	[31:0]	The details of timeout interrupt are shown in TMO[0] and TMO[10:8]. [0]-Timeout from not receiving ARP reply packet After timeout, the IP resends ARP request until ARP reply is received. [8]-Asserted when Rx data buffer is full. After that, all received packet are ignored until the buffer is not full. [9]-Asserted when UDP checksum of the received packet is error. [10]-Asserted when rx_axis_tuser shows error status.
01010b	PKL	Wr /Rd	[15:0]	UDP data length of each Tx packet in byte unit. The value must be aligned to 16-byte because bit[3:0] are not used. Valid from 16-8960. Default value is 1472 byte, which is the maximum size of non-jumbo frame and aligned to 16-byte. During running Send data command (Busy=1b), the user must not set this register. Similar to TDL/TDH register, the user does not need to set PKL register again if the next command uses the same packet length.
01101b	TDH	Wr	[15:0]	Define 16 upper bits (bit[47:32]) of 48-bit total Tx data length in byte unit, as described in TDL register.
01101b	TDH	Rd	[15:0]	16 upper bits of 48-bit remaining transfer length in byte unit which does not transmit, as described in TDL register.
01110b	SRV	Wr /Rd	[1:0]	00b: Client mode (default). When the RST register changes from 1b to 0b, the IP sends an ARP request to obtain the Target MAC address from the ARP reply returned by the target device. The IP busy signal is de-asserted to 0b after receiving the ARP reply. 01b: Server mode. When RST register changes from 1b to 0b, the IP waits for an ARP request from the target to obtain Target MAC address. After receiving the ARP request, the IP generates an ARP reply and then de-asserts the IP busy signal to 0b. 1Xb: Fixed MAC Mode. When the RST register changes from 1b to 0b, the IP updates all internal parameters and then de-asserts IP busy to 0b. Target MAC address is loaded through the DML/DMH register. Note: In Server mode, when RST register changes from 1b to 0b, the target device must resend an ARP request for the UD25G IP to complete the IP initialization process.
01111b	VER	Rd	[31:0]	IP version
10000b	DML	Wr /Rd	[31:0]	Define 32-bit lower target MAC address (bit [31:0]) for this IP when SRV[1:0]=1Xb (Fixed MAC). To update this value, the IP must be reset by RST register.
10001b	DMH	Wr /Rd	[15:0]	Define 16-bit upper target MAC address (bit [47:32]) for this IP when SRV[1:0]=1Xb (Fixed MAC). To update this value, the IP must be reset by RST register.

· UDP Stack

The UDP stack is responsible for controlling the modules involved in interfacing with the user and transferring packets via EMAC. The IP operation involves two phases - IP initialization and data transfer. After the RST register transitions from 1b to 0b, the initialization phase begins. The SRV[1:0] are used to set the initialization mode, which can be Client mode, Server mode, or Fixed MAC mode. The UDP stack reads the parameters from the Reg module and sets them in the Transmit and Receive blocks for packet transfer with the target device. Once initialization is complete, the IP enters the data transfer phase.

The UDP25G IP allows for simultaneous data transfer in both Tx and Rx directions with the target device. During sending data, the Busy signal is set to 1b. It is de-asserted to 0b once the sending process is completed. To transmit data, the user data is stored in the Tx data and Tx packet buffers. The Packet Builder uses the user-defined network parameters to build UDP header, and then the data of Tx data buffer is appended to the UDP packet. The Transmit block then sends the UDP packet to the target device via Ethernet MAC.

When the Receive block receives data, the Busy signal is not asserted. The extracted UDP data from the received packet is forwarded to the user without generating any packet to be returned to the target device. The Tx and Rx of UDP/IP are processed individually to achieve optimal performance in both directions.

Table 3: TxBuf/TxPac/RxBufBitWidth Parameter description

Value of BitWidth	Buffer Size	TxBufBitWidth	TxPacBitWidth	RxBufBitWidth
9	8kByte	Valid	Valid	Valid
10	16kByte	Valid	Valid	Valid
11	32kByte	Valid	No	Valid
12	64kByte	Valid	No	Valid

Transmit Block

Transmit block contains two buffers - Tx data buffer and Tx packet buffer – whose sizes can be adjusted through parameter assignment. The minimum size of these buffer is limited by the transmit packet size set by the PKL register. Data from the Tx data buffer is split into packets based on the packet size and stored in the Tx packet buffer. UDP header is constructed using the network parameters from the Reg module and then combined with the UDP data from the Tx packet buffer to form a complete UDP packet. The data in the Tx data buffer is flushed after the packet is transmitted to EMAC successfully. Once the Send data command is completed, the user can initiate the next command.

· Tx Data Buffer

The size of this buffer is determined by the “TxBufBitWidth” parameter of the IP, with valid value ranging from 9-12, which corresponds to the address size of a 128-bit buffer as shown in Table 3. To ensure sustainable transmission of data to EMAC, the buffer size should be at least twice the size of the Tx Packet Size set in the PKL register. By filling the buffer with data that is at least two times of the PKL value, the UDP25G IP will have a sufficient amount of data to transmit. This results in the best transmit performance on 25G Ethernet. Increasing the size of the buffer increases the possibility that at least two packet data will be available for UDP25G IP use.

· Tx Packet Buffer

The size of the buffer size is determined by the “TxPacBitWidth” parameter of the IP. Its valid range is 9-10, and the details of the parameter are shown in Table 3. To store at least one transmit packet, the buffer size must be larger than the Tx packet size set by the PKL register. Note that the maximum value of the PKL register is equal to the Tx Packet Buffer size (in bytes) minus 64. Configuring the buffer size to be greater than two times of PKL value does not provide any additional benefits.

· Packet Builder

The UDP packet is comprised of a header and data. The Packet builder first receives network parameters from the Reg module and uses them to construct the UDP header. The UDP and IP checksum are also calculated for the header. Once the header is fully constructed, it is combined with the data from the Tx packet buffer and then transmitted to the EMAC.

Receive Block

The Receive block contains the Rx data buffer, which stores the data received from the target device. The received data is stored in the buffer when the header in the packet matches the expected value, set by the network parameters inside the Reg module, and when the IP and UDP checksum are correct. If any of these conditions are not met, the received packet is rejected. Increasing the size of the Rx data buffer enhances the chances of avoiding lost packets due to user logic pausing for too long while reading data.

· Rx Buffer

This is temporary buffer that is used to hold incoming packets from EMAC in cases where the previous packet has not yet been completely processed.

· Packet Filtering

This module is responsible for verifying the header of the Rx packet to determine its validity. The packet will be valid if all following conditions are met.

(1) The network parameters must match the values set in the Reg module, such as the MAC address, IP address, and Port number.

(2) The packet must either be an ARP packet or a UDP/IPv4 packet.

(3) The IP header length must be valid, with the IP length being equal to 20 bytes.

(4) The IP data length matches to the UDP data length.

(5) Both the IP checksum and UDP checksum must be correct.

Note: UDP checksum is not verified for fragment packet.

(6) In case of fragment packet, the order of received packet must be correct. The packet is rejected when the fragment offset is skipped value.

· Packet Splitter

The purpose of this module is to extract UDP data from incoming packets and store it in the Rx data buffer, after removing the packet header.

· Rx Data Buffer

The size of the Rx data buffer is determined by the “RxBufBitWidth” parameter of the IP and can range from 9 – 12 (8KB to 64KB). It is recommended to set the buffer size to be equal to or greater than two times of the data size in the received packet. To ensure that data is not lost, user logic must read the data from the buffer to keep the free space size of the buffer to be greater than the data size in the received packet. Increasing the size of the buffer increases the possibility of having enough free space to store new data from the target device.

User Block

The core engine of the user module can be designed by state machine to set the command and the parameters through the Register interface. Additionally, the status can be monitored to ensure that the operation has been completed without any errors. The data path can also be connected to the FIFO for sending or receiving data with the IP.

10G/25G Ethernet System

Ethernet System comprises of Ethernet MAC and PCS/PMA hardware. When operating at 25G Ethernet, the user interface of Ethernet MAC is 64-bit AXI4 stream at 390.625 MHz. There are various solutions for 25G Ethernet System. Three solutions are described as below.

DG 10G25GEMAC IP Core

The first solution uses DG 10G25GEMAC IP and Xilinx PCS/PMA module. This solution is designed to optimize IP resource and has minimal latency time. The user interface of DG 10G25GEMAC IP can directly connect with UDP25G IP, and the PCS/PMA module can be created using the Xilinx tool’s IP wizard. The Xilinx IP core is no charge IP core. More information about DG 10G25GEMAC IP Core is available at

https://dgway.com/products/IP/10GEMAC-IP/dg_10g25gemacip_data_sheet_xilinx_en.pdf

Additionally, more details about the 10G/25G Ethernet PCS/PMA (BASE-R) are available at.

https://www.xilinx.com/products/intellectual-property/ef-di-25gemac.html

Note: This solution does not enable RS-FEC feature. Design Gateway provides another IP core, 25GEMAC/PCS with RS-FEC IP core which can find more details on our website.

10G/25G Ethernet Subsystem

The second solution uses the 10G/25G Ethernet Subsystem provided by Xilinx, which includes both Ethernet MAC and PCS/PMA. A small FIFO adapter logic is required to connect UDP25G IP and 10G/25G Ethernet Subsystem. More information about this IP is available at

https://www.xilinx.com/products/intellectual-property/ef-di-25gemac.html

Ethernet MAC Subsystem

The third solution uses the Ethernet MAC Subsystem available in Versal devices. Similar to the second solution, a small FIFO adapter logic is required to connect with the transceiver that needs to be generated using the IP wizard. More information about this IP core is available at

https://www.xilinx.com/products/intellectual-property/mrmac.html

Core I/O Signals

Descriptions of all parameters and I/O signals are provided in Table 4 - Table 6. The EMAC interface is 64-bit AXI4 stream interface.

Table 4: Core Parameters

Name	Value	Description
TxBufBitWidth	9-12	Setting Tx data buffer size. The value is referred to address bus size of this buffer.
TxPacBitWidth	9-10	Setting Tx packet buffer size. The value is referred to address bus size of this buffer.
RxBufBitWidth	9-12	Setting Rx data buffer size. The value is referred to address bus size of this buffer.

Table 5: User I/O Signals (Synchronous to Clk)

Signal	Dir	Description
Common Interface Signal
RstB	In	Reset IP core. Active Low.
Clk	In	User clock for running UDP25G IP. The frequency range is MacClk/2 – MacClk. When running with 25G Ethernet, MacClk frequency is 390.625 MHz. As a result, the valid range of Clk frequency is 195.3125 – 390.625 MHz.
User Interface
RegAddr[4:0]	In	Register address bus. Valid when RegWrEn=1b in Write process.
RegWrData[31:0]	In	Register write data bus. Valid when RegWrEn=1b.
RegWrEn	In	Register write enable. Valid at the same clock as RegAddr and RegWrData.
RegRdData[31:0]	Out	Register read data bus. Valid in the next clock after RegAddr is valid.
Busy	Out	IP busy status (0b-Idle, 1b-IP is busy when executing the initialization or send data process)
IntOut	Out	Timer interrupt. Asserted to high for 1 clock cycle when timeout is detected or Rx packet is ignored. More details of Interrupt status could be checked from TMO[10:0] register.
Tx Data Buffer Interface
UDPTxFfFull	Out	Asserted to 1b when Tx data buffer is full. User needs to stop writing data within 4 clock cycles after this flag is asserted to 1b.
UDPTxFfWrCnt[11:0]	Out	Data counter in 128-bit unit of Tx data buffer to show the amount of data in Tx data buffer.
UDPTxFfWrEn	In	Write enable to Tx data buffer. Asserted to 1b to write data to Tx data buffer.
UDPTxFfWrData[127:0]	In	Write data to Tx data buffer. Valid when UDPTxFfWrEn=1b.
Rx Data Buffer Interface
UDPRxFfRdCnt[11:0]	Out	Data counter of Rx data buffer to show the number of received data in 128-bit unit.
UDPRxFfLastRdCnt[3:0]	Out	Remaining byte of the last data in Rx data buffer when total amount of received data in the buffer is not aligned to 16-byte unit. User cannot read the data until all 16-byte data is received.
UDPRxFfRdEmpty	Out	Asserted to 1b when Rx data buffer is empty. User needs to stop reading data immediately when this signal is asserted to 1b.
UDPRxFfRdEn	In	Asserted to 1b to read data from Rx data buffer.
UDPRxFfRdData[127:0]	Out	Data output from Rx data buffer. Valid in the next clock cycle after UDPRxFfRdEn is asserted to 1b.

Table 6: EMAC I/O Signals (Synchronous to MacClk)

Signal	Dir	Description
MacClk	In	Receive clock from EMAC core which is equal to 390.625MHz for 25Gb Ethernet.
tx_axis_tdata[63:0]	Out	Transmitted data. Valid when tx_axis_tvalid=1b.
tx_axis_tkeep[7:0]	Out	The byte enable of transmitted data. Valid when tx_axis_tvalid=1b.
tx_axis_tvalid	Out	Valid signal of transmitted data.
tx_axis_tlast	Out	Control signal to indicate the final word in the frame. Valid when tx_axis_tvalid=1b.
tx_axis_tuser	Out	Control signal to indicate an error condition. This signal is always 0b.
tx_axis_tready	In	Handshaking signal. Asserted to 1b when tx_axis_tdata has been accepted. This signal must not be de-asserted to 0b when a packet is transmitting.
rx_axis_tdata[63:0]	In	Received data. Valid when rx_axis_tvalid=1b
rx_axis_tvalid	In	Valid signal of received data. rx_axis_tvalid must be asserted to 1b continuously for transferring a packet.
rx_axis_tlast	In	Control signal to indicate the final word in the frame. Valid when rx_axis_tvalid=1b.
rx_axis_tuser	In	Control signal asserted at the end of received frame (rx_axis_tvalid=1b and rx_axis_tlast=1b) to indicate that the frame has CRC error. 0b: normal packet, 1b: error packet.
rx_axis_tready	Out	Handshaking signal. Asserted to 1b when rx_axis_tdata has been accepted. rx_axis_tready is de-asserted to 0b for 1 clock cycles to be the gap size between each received packet.

Timing Diagram

IP Initialization

After the RST register value is changed from 1b to 0b, the initialization of UDP25G IP is initialized. Three modes can be executed, Client mode (SRV=00b), Server mode (SRV=01b), and Fixed MAC mode (SRV=1Xb). The information on each mode is presented in the timing diagram below.

Figure 3: IP Initialization in Client mode

As shown in Figure 3, in Client mode, the UDP25G IP sends an ARP request packet and waits for an ARP reply packet returned from the target device. Target MAC address is extracted from ARP reply packet. Upon completion, the Busy signal is de-asserted to 0b.

Figure 4: IP Initialization in Server mode

As shown in Figure 4, after reset process in Server mode is completed, the UDP25G IP waits for an ARP request packet from the target device. Upon receipt, the UDP25G IP generates an ARP reply packet. The Target MAC address is extracted from ARP request packet. Once the ARP reply packet has been transmitted, the Busy signal is de-asserted to 0b.

Figure 5: IP Initialization in Fixed mode

As shown in Figure 5, after reset process in Fixed MAC mode is completed, the UDP25G IP updates all parameters from the registers. The Target MAC address is loaded from DML and DMH register. Once this process is finished, the Busy signal is de-asserted to 0b.

Register Interface

The Register interface is responsible for setting and monitoring all control signals and network parameters during operation. The timing diagram of the interface is similar to that of Single-port RAM, which shares the address bus for write and read access, and has a read latency time of one clock cycle. A Register map of this interface is provided in Table 2.

As shown in Figure 6, to write to the register, the user sets RegWrEn to 1b with the valid values for RegAddr and RegWrData. Before setting RegWrEn to 1b, please confirm that RstB is de-asserted to 1b for at least 4 clock cycles. To read from the register, the user only sets RegAddr, and RegRdData becomes valid in the next clock cycle.

Figure 6: Register interface timing diagram

As shown in Figure 7, before setting the CMD register to initiate a new command operation, the Busy flag must be equal to 0b to confirm that IP is in Idle status. After setting the CMD register, the Busy flag is asserted to 1b and de-asserted to 0b when the command is completed.

Figure 7: CMD register timing diagram

Tx FIFO Interface

Tx FIFO interface provides two control signals for the flow control, the full flag (UDPTxFfFull) and the write data counter (UDPTxFfWrCnt). UDPTxFfWrCnt is updated after asserting UDPTxFfWrEn for two clock cycles. UDPTxFfFull serves as an indicator of when the internal buffer is almost full and is asserted before it reaches its capacity. It is recommended to pause sending data within four clock cycles after UDPTxFfFull is asserted. Figure 8 shows an example timing diagram for the Tx FIFO interface.

Figure 8: Tx FIFO interface timing diagram

(1) When the IP is in reset state (RST[0] register=1b), the full flag (UDPTxFfFull) is set to 1b, preventing data from being sent by the user. Once the reset is released (RST[0]=0b), UDPTxFfFull is set to 0b, allowing the user to write data to the IP.

(2) To write data, the user needs to set UDPTxFfWrEn to 1b along with the write data on UDPTxFfWrData signal.

(3) If UDPTxFfFull is set to 1b, the user must pause sending data by de-asserting UDPTxFfWrEn to 0b within 4 clock cycles.

Rx FIFO Interface

The Rx FIFO interface is used to retrieve data stored in the Rx data buffer. To determine if data is available for reading, the Empty flag (UDPRxFfEmpty) is monitored, and the read enable signal (UDPRxFfRdEn) is then asserted to access the data, like a typical FIFO read interface, as illustrated in as shown in Figure 9.

Figure 9: Rx FIFO interface timing diagram using Empty flag

(1) After the IP finishes reset process, there is no data in Rx data buffer and UDPRxFfEmpty is set to 1b.

(2) Check the UDPRxFfEmpty flag to confirm data availability. When data is ready (UDPRxFfEmpty=0b), set UDPRxFfRdEn to 1b to read data from the Rx data buffer.

(3) The UDPRxFfRdData signal is valid in the next clock cycle.

(4) Reading data must be immediately paused by setting UDPRxFfRdEn=0b when UDPRxFfEmpty is equal to 1b.

Figure 10: Rx FIFO interface timing diagram using read counter

When the user logic reads data in burst mode, the UDP25G IP provides a read data counter signal to indicate the total amount of data stored in the Rx data buffer in bytes. For instance, in Figure 10, there are five units of data available in the Rx data buffer. Therefore, the user can set UDPRxFfRdEn to 1b for five clock cycles to read all the data from the Rx data buffer. The latency time to update UDPRxFfRdCnt after setting UDPRxFfRdEn to 1b is two clock cycles.

EMAC Interface

EMAC interface of UDP25G IP utilizes a 64-bit AXI4-stream interface, but it has a limitation that it cannot pause data transmission before transmitting the end of the packet. To transmit a packet, the tx_axis_tready must be asserted to 1b while transmitting a packet. However, once the final data of the packet has been transferred, tx_axis_tready can be de-asserted to 0b to pause the transmission of the next packet.

Figure 11: Transmit EMAC interface timing diagram

(1) UDP25G IP asserts tx_axis_tvalid to 1b with the first data of the packet. All signals are latched until tx_axis_tready is asserted to 1b to accept the first data.

(2) After the first data is accepted by EMAC, tx_axis_tready must remain set to 1b to accept all remaining data in the packet from the UDP25G IP until the end of the packet. The IP sends all data of each packet continuously.

(3) tx_axis_tlast and tx_axis_tvalid are both asserted to 1b when the final data of the packet is transmitted.

(4) Once the end of the packet has been transferred, tx_axis_tready can be asserted to 0b to pause the transmission of the next packet.

The Receive EMAC interface also requires continuous receipt of packet data, similar to Transmit EMAC interface. The Valid signal must remain asserted at 1b from the start of the packet to the end of the packet without interruption, as shown in Figure 12.

Figure 12: Receive EMAC interface timing diagram

(1) The UDP25G IP detects the start of the receive frame when rx_axis_tvalid changes from 0b to 1b. In this cycle, the first data is valid on rx_axis_tdata. Afterward, rx_axis_tready is asserted to 1b to accept all data of this packet until the end of the packet. To continuously send the data of each packet, rx_axis_tvalid must remain set to 1b.

(2) The end of the packet is detected when rx_axis_tlast=1b and rx_axis_tvalid=1b. In this cycle, the final data of the packet is valid on rx_axis_tdata.

(3) After the final data of the packet has been transferred, UDP25G IP de-asserts rx_axis_tready for 1 clock cycle to complete the packet post-processing. Therefore, EMAC must support pausing data packet transmission for 1 clock cycle.

However, the user interface of Xilinx Ethernet (MAC) Subsystem may pause data transmission before the final data of each packet is transferred, which is incompatible with the continuous data transfer requirement of the UDP25G IP EMAC interface. Therefore, additional logic, including a small buffer, is necessary to store the data when the Xilinx Ethernet (MAC) Subsystem is not ready to transfer the data in each packet.

If the system design of UDP25G IP utilizes the DG 10G25GEMAC IP, it can directly connect without additional logic.

Example usage

Client mode (SRV[1:0] = 00b)

The steps to set the register for transferring data in Client mode are outlined below.

1) Set the RST register=1b to reset the IP.

2) Set the SML/SMH for MAC address, DIP/SIP for IP address, and DPN/SPN for port number.

3) Set RST register=0b to start the IP initialization process. The UDP25G IP will send an ARP request packet to get the Target MAC address from the ARP reply packet. The Busy signal is de-asserted to 0b after completing the initialization process.

4) a. For sending data, set TDL/TDH register (total transmit length) and PKL register (packet size). Then, set CMD register = 1b to start data transmission. The user can send the data to UDP25G IP via the TxFIFO interface before or after setting the CMD register. Once the command is finished, the Busy flag is de-asserted to 0b. The user can set a new value to the TDL/TDH/PKL register and then set CMD register = 1b to start the next transmission.

b. For receiving data, the user should monitor RxFIFO status and read the data until RxFIFO is empty.

Server mode (SRV[1:0] = 01b)

In Server mode, the MAC address is decoded from ARP request packet instead of ARP reply packet as in Client mode. However, the process for transferring data is the same as that of Client mode. The following steps illustrate an example of Server mode.

1) Set RST register=1b to reset the IP.

2) Set SML/SMH for MAC address, DIP/SIP for IP address, and DPN/SPN for port number.

3) Set RST register=0b to begin the IP initialization process by waiting for an ARP request packet to get the Target MAC address. The IP then creates an ARP reply packet to return to the target device. Once the initialization process is completed, the Busy signal is de-asserted to 0b.

4) The remaining step is the same as step 4 of Client mode

Fixed MAC mode (SRV[1:0] = 1Xb)

In Fixed MAC mode, tMAC Address of the target device is loaded from DML and DMH register. The process for transferring data is the same as that of Client and Server mode. The following steps provides an example of how to run UDP25G IP in Fixed MAC mode.

1) Set RST register=1b to reset the IP.

2) Set SML/SMH for MAC address of UDP25G IP, DML/DMH for MAC address of the target device, DIP/SIP for IP address, and DPN/SPN for port number.

3) Set RST register=0b to begin the IP initialization process. Once initialization is completed, the busy signal will be de-asserted to 0b.

4) The remaining step is the same as step 4 of Client mode

Verification Methods

The UDP25G IP Core functionality was verified by simulation and also proved on real board design by using KCU116/ZCU116 board and Silicom FB2CGHH@KU15P board.

Recommended Design Experience

User must be familiar with HDL design methodology to integrate this IP into their design.

Ordering Information

This product is available directly from Design Gateway Co., Ltd. Please contact Design Gateway Co., Ltd. For pricing and additional information about this product using the contact information on the front page of this datasheet.

Revision History

Revision	Date	Description
1.1	8-Mar-23	Support ZCU11, add UDPTxFfWrCnt, and update Figure 6.
1.0	2-Jun-21	New release