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1 Introduction
2 Hardware overview
2.1 25G Ethernet System (25G BASE-SR)
2.2 UDP25G-IP
2.3 CPU and Peripherals
2.3.1 AsyncAxiReg
2.3.2 UserReg
3 CPU Firmware on FPGA
3.1 Display parameters
3.2 Reset parameters
3.3 Send data test
3.4 Receive data test
3.5 Full duplex test
3.6 Function list in User application
4 Test Software on PC
5 Revision History
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UDP25G-IP reference design