Features Applications General Description Functional Description Control Block Reg UDP Stack Transmit Block Tx Data Buffer Tx Packet Buffer Packet Builder Receive Block Rx Buffer Packet Filtering Packet Splitter Rx Data Buffer User Block Low Latency 40G Ethernet Intel FPGA IP Core I/O Signals Timing Diagram. IP Initialization Register Interface Tx FIFO Interface Rx FIFO Interface MAC FIFO Interface Example usage Client mode (SRV[0]=?0?) Server mode (SRV[0]=?1?) Verification Methods Recommended Design Experience Ordering Information Revision History Return to Top