1 Introduction 2 Hardware design 2.1 Low Latency 40G Ethernet IP 2.2 UDPMacFfIF 2.3 UDP40G-IP 2.4 CPU and Peripherals 2.4.1 AsyncAvlReg 2.4.2 UserReg 3 CPU Firmware Sequence (FPGA) 3.1 Show parameters 3.2 Reset IP 3.3 Send data test 3.4 Receive data test 3.5 Full duplex test 3.6 Function list in User application 4 Test Software (PC) 5 Revision History Return to Top