1 Introduction 2 Hardware design 2.1 40G/50G Ethernet Subsystem. 2.2 UDP40G-IP 2.3 CPU and Peripherals 2.3.1 AsyncAxiReg 2.3.2 UserReg 3 CPU Firmware Sequence (FPGA) 3.1 Display parameters 3.2 Reset parameters 3.3 Send data test 3.4 Receive data test 3.5 Full duplex test 3.6 Function list in User application 4 Test Software on PC 5 Revision History Return to Top