1 Introduction 2 Hardware Overview 2.1 AsyncAxiReg 2.2 UserReg 2.3 IPv4 Routing 2.4 Ethernet Header Decapsulation Module 2.5 Ethernet Header Encapsulation Module 2.6 Ethernet Subsystem. 3 CPU Firmware 3.1 Set FPGA IP Address 3.2 Set FPGA Port Number 3.3 Set FPGA MAC Address 3.4 Set Gateway IP Address 3.5 Initialize TAI64 Timestamp 3.6 Set FPGA Private Key 3.7 Set WireGuard Interface Address IP 3.8 Set Peer Public Key 3.9 Set Allowed IP 3.10 Set Endpoint IP Address. 15 Set Endpoint IP Address 3.11 Set Pre-Shared Key. 15 Set Pre-Shared Key 3.12 Set Persistent Keepalive. 15 Set Persistent Keepalive 3.13 Show Ephemeral Private Key. 15 Show Ephemeral Private Key 3.14 Activate WireGuard. 16 Activate WireGuard 4 Revision History Return to Top