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1 Introduction
2 Hardware Overview
2.1 LAxi2Reg
2.2 AsyncAxiReg
2.3 UserReg
2.3.1 PacketParser Module
2.3.2 PacketTransfer Module
2.3.3 tCAM-IP Rule Initialize
2.3.4 tCAM-IP Key Search
2.3.5 PacketMover
2.4 LL10GEMAC
2.5 Xilinx Transceiver (PMA for 10GBASE-R)
2.6 PMARstCtrl
3 CPU Firmware
3.1 Show Access List
3.2 Add Access List Entry
3.3 Move Access List Entry
3.4 Remove Access List Entry
3.5 Clear All Access List Entries
3.6 Show Network Status
3.7 Configure Comparison Mode
4 Revision History
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UDP Packet Switching Reference Design