DesignGateway Hot! News December 2018

	[SDLink] ultra-low cost & programming configuration file for the largest FPGA in only a few seconds
	SDLink is a high-speed FPGA configuration module which stores configuration data on microSD card. Compared to standard configuration ROM, the unit price per bit is 1/1000. SDLink solves the problem of programming time for Huge scale FPGAs. You can just swap microSD card to update FPGA configuration data easily and quickly in the field. Learn more about SDLink SDLink Demo Video on YouTube

Overwhelming Cost Performance SDLink attaches 2GBytes microSD or 16GBytes SDHC microSD card which is unlimited capacity for FPGA configuration data. The cost performance is up to 1/1000 compared with the conventional configuration ROM. (*Price per bit. Comparison between 128Mbit configuration ROM and SDLink 16GB lot) Learn more about SDLink SDLink Demo Video on YouTube Learn more about SDLink ultra low cost Configuration Module Drastic short programming time for large scale FPGAs The programming time for 42MBytes configuration data is., Just 3 Seconds!! Moreover, the programming cable is unnecessary. Super high-speed programming demo on YouTube SDLink Demo on YouTube Learn more about super high-speed programming & configuration of SDLink SDLink is available on Mouser You can purchase SDLink from Mouser Electronics, Inc. MOUSER SDLink Production page News FPGA training Camp in Bangkok DesignGateway will arrange 2nd Digital Design with FPGA Camp (DD-Camp) at Chulalongkorn University in Thailand on 20 December 2018 - 4 January 2019. DesignGateway inspire and encourage Thai’s Engineering Students to come into the field of Programmable Digital Design. DD-Camp Facebook page Technical Updates NVMe-IP Xilinx NVMe IP Datasheet Rev3.2 - Updated NVMe IP Reference Design Document Rev3.1 - Updated NVMe IP Demo Instruction Document Rev3.1 - Updated Intel NVMe IP Datasheet Rev3.1 - Updated NVMe IP Reference Design Document Rev3.1 - Updated SATA-IP Xilinx exFAT IP for SATA IP Datasheet Rev1.0 - New exFAT IP for SATA IP Reference Design Document Rev1.0 - New exFAT IP for SATA IP Demo Instruction Document Rev1.0 - New Intel exFAT IP for SATA IP Datasheet Rev1.0 - New exFAT IP for SATA IP Reference Design Document Rev1.0 - New exFAT IP for SATA IP Demo Instruction Document Rev1.0 - New UDP1G-IP Xilinx UDP1G IP Reference Design Document Rev1.1 - Updated UDP1G IP Demo Instruction Document Rev1.1 - Updated SDLink SDLink Datasheet Rev2.0 - Updated SDLink User Manual Rev2.1 - Updated SDLink Demo Video (YouTube) - Updated Events SEMICON Japan 2018 Date: Dec 12-14, 2018 Place: Tokyo Big Sight, Japan More Information INTERNATIONAL TECHNICAL EXHIBITION ON IMAGE TECHNOLOGY AND EQUIPMENT 2018 Date: Dec 5-7, 2018 Place: PACIFICO YOKOHAMA, Japan More Information 2018 International Printed Circuit & APEX South China Fair Date: Dec 5-7, 2018 Place: Shenzhen Convention & Exhibition Center, China More Information Privacy Protection Policy DesignGateway recognizes the importance of personal information protection, and strive to protect personal information. We absolutely do not transfer it to a third party. Distributed stop / Address change / Register If you do not wish us to send or if your E-mail address is changed, please contact following page. https://dgway.com/mailmaga_E.html Publisher DesignGateway Co., Ltd. http://www.design-gateway.com/ Mail：ip-sales@design-gateway.com | About Us| Contact| (c) 2018 Design Gateway Co., Ltd.