DesignGateway Hot! News
April 2020
Super Low Latency Networking IP cores for Fintech



Design Gateway’s Low Latency Networking IP is designed from the ground up for very low latency requirements. Especially, FinTech applications such as high-frequency trading (HFT), high speed trading (HST), Market Data Processing and Tick-to-Trade (T2T) systems. We can provide total solutions for low latency Networking IP cores and FPGA logic customization for application specific requirements.

Learn more about Low Latency Networking IP for Fintech

Overview (UDP10GTx/Rx)
  • All Hard wired Logic
  • Minimum Latency : 3.2 ns (Tx: 1 cycle @ 312.5 MHz)
  • CPU less and no external memory required
  • Support Multicast and Unicast
  • Support Multi-session up to 4 sessions (More sessions can be customized)
  • Join/Leave group by IGMPv2 protocol
  • Direct connect with super low latency DG 10GbE MAC core (LL10GEMAC-IP)
    • Tx Latency : 16 ns (5 cycle @ 312.5 MHz)
    • Rx Latency : 9.6 ns (3 cycle @ 312.5 MHz)
  • Customizable for other user-specific protocols Contact Us
Technical Updates
UDP1G-IP
TOE40G-IP
TOE1G-IP
NVMeG3-IP
News
UDP1G IP Introduction on YouTube
The introduction video clip of CPU-less all hardwired UDP1G IP core is available on YouTube.
Subscribe to DG Channel on YouTube

UDP1G IP introduction
on YouTube

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Publisher
DesignGateway Co., Ltd.
https://dgway.com/
Mail:ip-sales@design-gateway.com
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