本文へスキップ

The Expert of IP Core & Embedded


Security & Search IP Coreshigh-throughput & minimum latency

Design Gateway provides security IP cores and search IP core that are highly compatible with DG's ultra-high-speed storage and network IP cores. By implementing highly reliable security features for ultra-high-speed data transfer, it becomes possible to develop even higher value-added applications.

for Mission-critical Applications for Secure
Storage Application
for Secure
Network Application
High throughput Encryption IP High throughput Security IP 200M SPS
Search Engine
TLS IPTLS1.3 IP AES256XTS IPAES256-XTS IP AES256GCM IPAES256-GCM IP AES256 IPAES256/128 IP SHA256 IPSHA256 IP tCAM IPtCAM IP

Introduction Video


Security IPs Introduction Video
Blogs [Security]

Features of Security IPs

  • No CPU or external memory required
  • Resource-saving and compact
  • Easy to use with a simple interface
  • Ultra-high-speed and ultra-low latency
  • Royalty-free license
  • Easily inpremented into user logic
  • Flexible customization options Contact Us

Product Brochures

for AMD (Rev2.6EX) | for Altera (Intel) (Rev2023Q4)

Technical Updates

Technical & Marketing Document Updates

Security IP core series Design Guide



CPU-less TLS1.3 Offload IP core for FPGA Acceleration [TLS1.3 IP]

TLS1.3 IP (Transport Layer Security IP) is the CPU-less & High-performance TLS v1.3 protocol engine for FPGA Acceleration with no CPU and external memory required. Providing maximum Gigabit Ethernet throughput for highly secure data transmission over 1G/10G/25G/100G network. Protect your valuable data from potential security breaches by using TLS secure transmission now! Especially, in Industrial IoT & Automation, Aerospace & Defense Applications.

Our TLS 1.3 IP core demo can successfully demonstrate very high throughput HTTPS Upload and Download with standard web server by pure hardware logic on FPGA.

YouTube Video


TLS1.3 Server 10G IP Introduction & Performance Demo

Key Features

  • CPUless & No external memory required
  • Key exchange : X25519
  • Derive key : HKDF with SHA384
  • Encryption/decryption : AES256GCM
  • Self-signed Certificate : RSA2048
  • Support Ethernet speed 1G/10G/25G and 100G(TBA or Please contact us)

Evaluation Demo Documents

IP core Document Name Altera (Intel) AMD Video
TLS 1.3 Server
10G IP
Datasheet Contact us Rev1.00
Reference Design Document Rev1.00
Demo Instruction Document Rev1.00
Free Evaluation Demo file ZCU102
TLS 1.3 Client
10G IP
Datasheet Contact us Rev1.02
Reference Design Document Rev1.02
Demo Instruction Document Rev1.02
Free Evaluation Demo file ZCU106

TLS 1.3 Client
1G IP
Datasheet Contact us
Reference Design Document
Demo Instruction Document Rev1.01
Free Evaluation Demo file AC701

Security for Storage Applications [AES256-XTS IP]

High throughput & Super Low Latency for secure storage applications

AES256-XTS IP Core (AES256XTSIP) implement the advanced encryption standard (AES) with XEX Tweakable Block Cipher with Ciphertext Stealing (XTS) which is widely used in protecting the confidentiality of data on storage devices.

YouTube Video


AES256-XTS IP Introduction & Demo

Features

  • Support AES-XTS mode
  • Support 256-bit key size
  • Support input data width128-bit
  • Support Ciphertext Stealing
  • Peak throughput rate at 128 Mbits/MHz
  • High-throughput, up to 51.2 Gbps @400MHz

Technical Documents

Document Name Altera (Intel) AMD
Datasheet Rev1.01 Rev1.01
Reference Design Document Rev1.00 Rev1.00
AES-IP core series Design Guide Rev1.00 Rev1.00
Demo Instruction Document Rev1.00 Rev1.00
Free Evaluation Demo file
* Ask Password to download
Agilex™ F-series
Arria® 10 SX
ZCU106

AES256-XTS-STG IP implement the advanced encryption standard (AES) with XEX (XOR Encrypt XOR) tweakable block cipher which operates sequences of complete blocks and is widely used in protecting the confidentiality of data on various storage devices with interfaces such as NVMe and SATA. We also have a lineup of "2X" ideal for NVMe PCIe Gen4, and "4X", supported Gen5.

Features

  • Support AES-XTS mode
  • Support 256-bit key size
  • Support input data width128-bit
  • Support Auto Increment Iv every 512-byte Mode
  • Customized service for following features
    • Modify block size for Iv auto increment mode.

YouTube Video


Enhancing NVMe SSD Security
with AES256-XTS-STG Encryption

  • Peak throughput rate
    • XTS-STG : 128 Mbits/MHz
    • XTS-STG-2X : 256 Mbits/MHz
    • XTS-STG-4X : 512 Mbits/MHz
  • High-throughput
    • XTS-STG : 35.2 Gbps @275MHz
    • XTS-STG-2X : 85.3 Gbps @333MHz
    • XTS-STG-4X : 204.8 Gbps @400MHz.

Technical Documents

Document Name Altera (Intel) AMD
AES256-XTS-STG IP Datasheet Rev1.00 Rev1.01
AES256-XTS-STG IP
Reference Design Document
Rev1.00 Rev1.00
AES256-XTS-STG IP with NVMe-IP
Reference Design Document
Rev1.01 Rev1.01
Demo Instruction Document Rev1.00 Rev1.01
Free Evaluation Demo file * Ask Password to download
AES256-XTS-STG IP (for NVMe Gen3) Arria® 10 SX
AES256-XTS-STG-2X IP (for NVMe Gen4) VCK190
AES256-XTS-STG-4X IP (for NVMe Gen5) Agilex™ I-series VPK120

Security for Networking Applications [AES256-GCM IP]

High throughput & Super Low Latency for secure communication applications.

AES256-GCM IP core implement the advanced encryption standard (AES) with 256-bit key in Galois/Counter Mode (GCM) which is widely used for Authenticated Encryption with Associated Data (AEAD) application. This IP is suitable to work together with Low Latency TOE10G IP core for high performance, low latency and secure communication applications.

YouTube Video


AES256-GCM100G IP Introduction & Demo

Features

  • Support AES-GCM mode standard.
  • Support 256-bit key size, 96-bit iv size.
  • Support zero-length AAD or data input.
  • Peak throughput rate at 512 Mbits/MHz (AES256-GCM-100G IP)
  • High-throughput
    • AES256-GCM-100G IP Speed up to 138.24 Gbps @270MHz
    • AES256-GCM-10G25G IP Speed up to 28.16 Gbps @220MHz
    • AES256-GCM1G IP Speed up to 3.2 Gbps @350MHz

Technical Documents

IP core Document Name Altera (Intel) AMD
AES256-GCM
100G IP
Datasheet Rev1.00 Rev1.00
Reference Design Document Rev1.00 Rev1.00
Demo Instruction Document Rev1.00 Rev1.01
Free Evaluation Demo file
* Ask Password to download
Agilex™ F-series
Arria® 10 SX
ZCU106
KCU116

AES256-GCM
10G25G IP
Datasheet Rev1.03 Rev1.04
Reference Design Document Rev1.03 Rev1.03
Demo Instruction Document Rev1.03 Rev1.04
Free Evaluation Demo file
* Ask Password to download
Agilex™ F-series
Arria® 10 SX
ZCU106

AES256-GCM
1G IP
Datasheet Rev1.00
Reference Design Document Rev1.00
Demo Instruction Document Rev1.00
Free Evaluation Demo file
* Ask Password to download
ZCU106

Common AES-IP core series Design Guide Rev1.00

High Throughput Encryption [AES-256SS IP | AES-256 IP | AES-128 IP]

  

AES-256SS IP specializes in ultra-high throughput and ultra-low latency. IP computes 128-bit data blocks in every 1 clock cycle. Delivering 128Mbps throughput per 1MHz such as 51.2 Gbps @ 400MHz.


AES-128 IP is 1st member of Advanced Encryption Standard (FIPS-197) IP Series, designed to support ECB mode for both encryption and decryption. AES128-IP computes 128-bit data blocks within constant 11 clock cycles. Delivering 11.6Mbps throughput per 1MHz such as 5.8 Gbps @ 500MHz.

AES Encryption IP Series is designed to enhance security features of existing Data Storage and Networking IP Cores. Enabling more opportunity for inventing the secure, efficient and high performance applications.

Features

YouTube Video

  • Support AES ECB mode standard.
  • Key size
    • AES-128 IP: 128 bit
    • AES-256 IP: 256 bit
  • Support input data width128-bit.
  • High-Throughput rate
    • AES-256SS IP: 51.2 Gbps @400MHz, 128 Mbits/MHz
    • AES-128 IP: 5.8 Gbps @500MHz, 11.6 Mbits/MHz
    • AES-256 IP: 4.26 Gbps @500MHz, 8.53 Mbits/MHz
  • Low Latency
    • AES-256SS IP: 15 clock cycles for 128-bit data calculation
    • AES-128 IP: 11 clock cycles for 128-bit data calculation
    • AES-256 IP: 15 clock cycles for 128-bit data calculation

AES-128 IP Introduction

Technical Documents

IP core Document Name Altera (Intel) AMD

AES-256SS IP
Datasheet Rev1.03 Rev1.04
Reference Design Document Rev1.02 Rev1.02
Demo Instruction Rev1.02 Rev1.02
Free Evaluation Demo file
* Ask Password to download
Agilex™ F-series
Arria® 10 SX
ZCU106

AES-256 IP
Datasheet Rev1.03 Rev1.04
Reference Design Document Rev1.03 Rev1.02
Demo Instruction Rev1.03 Rev1.02
Free Evaluation Demo file
* Ask Password to download
Agilex™ F-series
Arria® 10 SX
ZCU106

AES-128 IP
Datasheet Rev1.03 Rev1.03
Reference Design Document Rev1.03 Rev1.03
Demo Instruction Rev1.02 Rev1.02
Free Evaluation Demo file
* Ask Password to download
Agilex™ F-series
Arria® 10 SX
ZCU106

Common AES-IP core series Design Guide Rev1.00

High Throughput Security [SHA-256 IP]

 

SHA-256 IP is an optimized and efficient implementation of a secure hash algorithm SHA-256 specified in FIPS 180-4 standard. SHA256-IP can process 512-bit data blocks in just 65 clock cycles. Delivering 7.875Mbps throughput per 1MHz clock such as 2.362 Gbps throughput @ 300MHz. * tentative

SHA-256 is one of the most secure and practically unbreakable hashing functions which is most popular to use in various applications such as secure password hashing, digital signature, SSL/TLS certificate and Bitcoin cryptocurrency.

Together with Design Gateway's data storage and networking IP, SHA256-IP enables more opportunity for inventing the secure, efficient and high performance applications.

 

Features

YouTube Video

  • Support SHA 256-bit standard function
  • Support input data length up to 261-1 bytes (264-8 bits)
  • Super high throughput rate at 65 clocks per 64 bytes data
  • Hash speed up to 2.362 Gbps @ 300MHz * tentative
  • Simple user interface signals as same as FIFO interface
  • Small Resource Consumption

SHA-256 IP introduction

Technical Documents

Document Name Altera (Intel) AMD
Datasheet Rev1.00 For AMD devices,
please Contact Us
Demo Instruction Rev1.00
Evaluation Demo file Arria 10 SX
* Ask Password to download


HIgh-speed & Low latency Search Engine [tCAM IP]

tCAM-IP is a high performance, extremely low latency and highly configurable ternary content-addressable memory IP. tCAM-IP can make deterministic search at 200MSPS continuously speed with constant latency at 7 clock cycles. It can achieve matching/filtering performance at 200,000,000 packets per second over 40G/100G Ethernet. It is ideal for variant applications such as network packet filtering/forwarding, intelligent switch/router, deep packet inspection and network security application. We can provide tCAM-IP custom reference design together with TOE40G/10G/1G-IP, UDP40G/10G/1G-IP, EMAC-IP based on customer requirements. Contact Us
Altera (Intel) AMD
tCAM IP for Altera (Intel) tCAM IP for AMD

YouTube Video


tCAM-IP introduction

tCAM-IP performance demo on Arria 10 SX

tCAM-IP performance demo on Arria 10 SX

Blog: What's TCAM?


Alliance Partner




Design Gateway Co., Ltd.

Head Office
3-23-17 Naka-cho, Koganei, Tokyo, JAPAN
R&D
89/26 Amornpan 205 Tower1, 18th floor, Ratchadapisek7 (Nathong) Alley, Ratchadapisek Road, Din Daeng, Bangkok, 10400 THAILAND