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Features of Security IPs

• No CPU or external memory required
• Resource-saving and compact
• Easy to use with a simple interface
• Ultra-high-speed and ultra-low latency
• Royalty-free license
• Easily inpremented into user logic
• Flexible customization options Contact Us

Product Brochures

Technical Updates

Security IP core series Design Guide

• AES-IP core series Design Guide

TLS1.3 IP (Transport Layer Security IP) is the CPU-less & High-performance TLS v1.3 protocol engine for FPGA Acceleration with no CPU and external memory required. Providing maximum Gigabit Ethernet throughput for highly secure data transmission over 1G/10G/25G/100G network. Protect your valuable data from potential security breaches by using TLS secure transmission now! Especially, in Industrial IoT & Automation, Aerospace & Defense Applications.

Our TLS 1.3 IP core demo can successfully demonstrate very high throughput HTTPS Upload and Download with standard web server by pure hardware logic on FPGA.

YouTube Video

TLS1.3 Server 10G IP Introduction & Performance Demo

Key Features

• Support TLS1.3 cipher suite: TLS_AES_256_GCM_SHA384
  • Key exchange : X25519
  • Derive key : HKDF with SHA384
  • Encryption/decryption : AES256GCM
• Signature algorithm:
  • rsa_pss_rsae_sha256 with 2048-bit RSA public key
  • ecdsa_secp256r1_sha256
• Recommended Clock Frequency: At least 180 MHz for maximum throughput
• Customized service for following features
  • Maximum fragment length and buffer size extension
  • Certificate size extension
• Listed in the AMD Adaptive Computing Partner Solutions

Hardware-Accelerated Digital Signature Verification for High-Security Systems

The ECDSA256V-IP core implements Elliptic Curve Digital Signature Algorithm (ECDSA) verification on the NIST P-256 curve, providing a high-performance, hardware-only solution for secure authentication in modern communication and IoT systems. It eliminates CPU load by performing full signature verification entirely in hardware, without requiring software or external memory.

This IP is compliant with FIPS 186-4 and validated with official NIST test vectors, ensuring accuracy and standard compliance.

YouTube Video

Key Features

• Pure hardware ECDSA signature verification ? no CPU, software, or external memory required
• Supports NIST P-256 curve with 256-bit message digest
• Performance: Over 100 verifications per second @240 MHz
• Compliant with FIPS 186-4 standard
• Supports other elliptic curves on request
• Proven functionality through NIST test vector verification and SSL certificate validation demo

High throughput & Super Low Latency for secure communication applications.

The AES256-GCM IP core implements the Advanced Encryption Standard (AES) with a 256-bit key in Galois/Counter Mode (GCM), which is widely used for Authenticated Encryption with Associated Data (AEAD) applications. This IP has been verified against the official NIST (National Institute of Standards and Technology) test vectors, as defined in SP 800-38D, ensuring standards compliance. It is well-suited for high-performance, low-latency, and secure communication applications.

YouTube Video

Validating DG’s AES256GCM IP with NIST Test Vectors

AES256-GCM100G IP Introduction & Demo

Features

• Support AES-GCM mode standard.
• Support 256-bit key size, 96-bit iv size.
• Support zero-length AAD or data input.
• Peak throughput rate at 512 Mbits/MHz (AES256-GCM-100G IP)
• High-throughput
  • AES256-GCM-100G IP Speed up to 138.24 Gbps @270MHz
  • AES256-GCM-10G25G IP Speed up to 28.16 Gbps @220MHz
  • AES256-GCM1G IP Speed up to 3.2 Gbps @350MHz
• Proven high reliability and accuracy through verification with official NIST test vectors. Watch Demo Video
• Free evaluation project is available from Github
• Listed in the AMD Adaptive Computing Partner Solutions

The ChaCha20-Poly1305 IP core implements the ChaCha20 stream cipher together with the Poly1305 message authentication code (MAC), following the IETF standard for Authenticated Encryption with Associated Data (AEAD).

ChaCha20 provides high-speed encryption and decryption with strong resistance against timing attacks, while Poly1305 ensures message authentication and integrity. Together, they form a widely adopted AEAD construction. The core supports a 256-bit key size and a 96-bit IV size. It also supports zero-length Additional Authenticated Data (AAD) or plaintext input, making it flexible for a wide range of secure applications.

YouTube Video

ChaCha20-Poly1305 IP
Introduction & Demo

Features

• Fully compliant with ChaCha20Poly1305 AEAD standard (RFC 8439)
• Supports 256-bit key size and 96-bit IV
• Supports zero-length AAD or data input
• Peak throughput rate of 64 Mbits/MHz

High throughput & Super Low Latency for secure storage applications

AES256-XTS-STG IP implement the advanced encryption standard (AES) with XEX (XOR Encrypt XOR) tweakable block cipher which operates sequences of complete blocks and is widely used in protecting the confidentiality of data on various storage devices with interfaces such as NVMe and SATA. We also have a lineup of "2X" ideal for NVMe PCIe Gen4, and "4X", supported Gen5.

Features

• Support AES-XTS mode
• Support 256-bit key size
• Support input data width128-bit
• Support Auto Increment Iv every 512-byte Mode
• Customized service for following features
  • Modify block size for Iv auto increment mode.
• Free evaluation project is available from Github
• Listed in the AMD Adaptive Computing Partner Solutions

YouTube Video

Enhancing NVMe SSD Security
with AES256-XTS-STG Encryption

• Peak throughput rate
  • XTS-STG : 128 Mbits/MHz
  • XTS-STG-2X : 256 Mbits/MHz
  • XTS-STG-4X : 512 Mbits/MHz
• High-throughput
  • XTS-STG : 35.2 Gbps @275MHz
  • XTS-STG-2X : 85.3 Gbps @333MHz
  • XTS-STG-4X : 204.8 Gbps @400MHz.

YouTube Video

AES256-XTS IP Introduction & Demo

Features

• Support AES-XTS mode
• Support 256-bit key size
• Support input data width128-bit
• Support Ciphertext Stealing
• Peak throughput rate at 128 Mbits/MHz
• High-throughput, up to 51.2 Gbps @400MHz
• Listed in the AMD Adaptive Computing Partner Solutions

AES-256SS IP specializes in ultra-high throughput and ultra-low latency. IP computes 128-bit data blocks in every 1 clock cycle. Delivering 128Mbps throughput per 1MHz such as 51.2 Gbps @ 400MHz.

AES-128 IP is 1st member of Advanced Encryption Standard (FIPS-197) IP Series, designed to support ECB mode for both encryption and decryption. AES128-IP computes 128-bit data blocks within constant 11 clock cycles. Delivering 11.6Mbps throughput per 1MHz such as 5.8 Gbps @ 500MHz.

AES Encryption IP Series is designed to enhance security features of existing Data Storage and Networking IP Cores. Enabling more opportunity for inventing the secure, efficient and high performance applications.

Features

YouTube Video

• Support AES ECB mode standard.
• Key size
  • AES-128 IP: 128 bit
  • AES-256 IP: 256 bit
• Support input data width128-bit.
• High-Throughput rate
  • AES-256SS IP: 51.2 Gbps @400MHz, 128 Mbits/MHz
  • AES-128 IP: 5.8 Gbps @500MHz, 11.6 Mbits/MHz
  • AES-256 IP: 4.26 Gbps @500MHz, 8.53 Mbits/MHz
• Low Latency
  • AES-256SS IP: 15 clock cycles for 128-bit data calculation
  • AES-128 IP: 11 clock cycles for 128-bit data calculation
  • AES-256 IP: 15 clock cycles for 128-bit data calculation
• Listed in the AMD Adaptive Computing Partner Solutions

Features

• Supports SHA-224, SHA-256, SHA-384, SHA-512, SHA-512/224, and SHA-512/256 algorithms.
• Accepts input message lengths up to 2⁶⁴-8 bits (SHA-224/256) and 2¹²⁸-8 bits (SHA-384/512)
• High-performance architecture with only:
  • 65 cycles per 64-byte block for SHA-224/256.
  • 81 cycles per 128-byte block for SHA-384/512.
• Achieves throughput up to:
  • 1.969 Gbps @ 250 MHz for SHA-256
  • 3.160 Gbps @ 250 MHz for SHA-512
• User data interface: Utilizes a 32-bit AXI4 stream interface.

Technical Documents

Features

YouTube Video

• Support SHA 256-bit standard function
• Support input data length up to 2⁶¹-1 bytes (2⁶⁴-8 bits)
• Super high throughput rate at 65 clocks per 64 bytes data
• Hash speed up to 2.362 Gbps @ 300MHz ^{_{* tentative}}
• Simple user interface signals as same as FIFO interface
• Small Resource Consumption

Technical Documents

tCAM-IP is a high-performance, extremely low-latency, and highly configurable ternary content-addressable memory IP. tCAM-IP can make continuous deterministic search at 400 MSPS with constant latency of 7 clock cycles. It can achieve matching/filtering performance of 400,000,000 packets per second over Gigabit Ethernet. It is ideal for various applications such as network packet filtering/forwarding, intelligent switch/router, deep packet inspection, and network security applications. We can provide tCAM-IP custom reference designs together with TOE-IP core series, UDP-IP core series, and EMAC-IP based on customer requirements. Contact Us

YouTube Video