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The Expert of IP Core & Embedded

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Application Specific IP Cores (AS-IP)Ultra high-speed and minimum latency

Design Gateway Co., Ltd. provides Application Specific IP cores (AS-IP) based on rich experience from provider of high-speed Storage and Networking IP Cores (Giga Bit IP cores). The AS-IP focus applications which require high-speed and low latency such as finance and network equipments.

Low Latency Networking IP┃tCAM IP
  • Ultra High-speed and Low latency
  • Support the latest FPGAs
  • Provide flexible customization matched with system requirements. Contact Us

Low Latency Networking IP

Design Gateway’s Low Latency Networking IP is designed from the ground up for very low latency requirements. Especially, FinTech applications such as high-frequency trading (HFT), high speed trading (HST), Market Data Processing and Tick-to-Trade (T2T) systems. We can provide total solutions for low latency Networking IP cores and FPGA logic customization for application specific requirements.
Learn more: Low Latency Networking IP for Intel Learn more: Low Latency Networking IP for Xilinx
Presentation for Intel Presentation for Xilinx

Example Block diagram for Fintech
Design Gateway Provides optimized IP & Customized service for Fintech
  • UDP10GTx / UDP10GRx, TOE10GLL, LL10GEMAC
  • Customized service

tCAM IP

tCAM-IP is a high performance, extremely low latency and highly configurable ternary content-addressable memory IP. tCAM-IP can make deterministic search at 200MSPS continuously speed with constant latency at 7 clock cycles. It can achieve matching/filtering performance at 2,000,000 packets per second over 40G/100G Ethernet. It is ideal for variant applications such as network packet filtering/forwarding, intelligent switch/router, deep packet inspection and network security application. We can provide tCAM-IP custom reference design together with TOE40G/10G/1G-IP, UDP40G/10G/1G-IP, EMAC-IP based on customer requirements.

Features

  • Key width 32/24/16/8 bits
  • Up to 512K rule entries
  • Searching latency is constant at 7 clock cycles
  • Up to 200 MSPS @ 200MHz searching speed, 1,000,000 Search/MHz
  • Easy to customize rule table memory
  • Simple rule table memory setup and user interface signals
  • Free evaluation demo combined with DG TOE1G-IP core is available

Example Block Diagram for Network switching & filtering application
Datasheet for Intel Datasheet for Xilinx (to be released)
Demo Instruction for Arria 10 SX (coming soon)



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Design Gateway Co., Ltd.

Head Office
3-23-17 Naka-cho, Koganei, Tokyo, JAPAN
R&D
54 BB Building 14th Fl., Room No. 1402 Sukhumvit 21 Rd. (Asoke), Klongtoey-Nua, Wattana, Bangkok 10110,THAILAND