Design Gateway Co., Ltd. provides Application Specific IP cores (AS-IP) based on rich experience from provider of high-speed Storage and Networking
IP Cores (Giga Bit IP cores). The AS-IP focus applications which require
high-speed and low latency such as finance and network equipments. |
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Intel | Xilinx | ||
Learn more: LL Networking IP for Intel | Learn more: LL Networking IP for Xilinx | ||
Presentation for Intel | Presentation for Xilinx | ||
Turnkey Accelerator System | |||
Key Features
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Accelerated High Frequency Trading (HFT) reference design![]() * Click to show more detail We provides super low latency IPs and customized service for Fintech |
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YouTube Video |
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![]() LL Networking IP introduction |
![]() TOE10GLL-IP 32 Session Demo |
![]() LL UDP10GRx-IP 16 Session Demo |
![]() LL 10G EMAC-IP with Xilinx’s AATDemo |
Articles |
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Intel | Xilinx | ||
tCAM IP for Intel | tCAM IP for Xilinx | ||
YouTube Video |
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![]() tCAM-IP introduction |
![]() tCAM-IP performance demo on Arria 10 SX |
![]() tCAM-IP performance demo on Arria 10 SX |
![]() Blog: What's TCAM? |
SHA-256 IP is an optimized and efficient implementation of a secure hash algorithm SHA-256 specified in FIPS 180-4 standard. SHA256-IP can process 512-bit data blocks in just 65 clock cycles. Delivering 7.875Mbps throughput per 1MHz clock such as 2.362 Gbps throughput @ 300MHz. * tentative
SHA-256 is one of the most secure and practically unbreakable hashing functions which is most popular to use in various applications such as secure password hashing, digital signature, SSL/TLS certificate and Bitcoin cryptocurrency.
Together with Design Gateway's data storage and networking IP, SHA256-IP enables more opportunity for inventing the secure, efficient and high performance applications.
Features |
YouTube Video |
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![]() SHA-256 IP introduction |
Technical Documents |
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Intel | Xilinx |
Datasheet for Intel Rev1.00 | |
Demo Instruction for Intel Rev1.00 | For Xilinx devices, please Contact Us |
Evaluation Demo file for Arria 10 SX |
![]() AES-128 IP is 1st member of Advanced Encryption Standard (FIPS-197) IP Series, designed to support ECB mode for both encryption and decryption. AES128-IP computes 128-bit data blocks within constant 11 clock cycles. Delivering 11.6Mbps throughput per 1MHz such as 5.8 Gbps @ 500MHz. ![]() AES-256SS IP specializes in ultra-high throughput and ultra-low latency. IP computes 128-bit data blocks in every 1 clock cycle. Delivering 128Mbps throughput per 1MHz such as 51.2 Gbps @ 400MHz. AES Encryption IP Series is designed to enhance security features of existing Data Storage and Networking IP Cores. Enabling more opportunity for inventing the secure, efficient and high performance applications. |
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Features |
YouTube Video |
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![]() AES-128 IP Introduction |
IP core | Document Name | Intel Agilex™ F-series Arria® 10 SX |
Xilinx ZCU106 |
![]() AES-256SS IP |
Datasheet | Rev1.02 | Rev1.03 |
Reference Design Document | Rev1.02 | Rev1.03 | |
Demo Instruction | Rev1.02 | Rev1.03 | |
Free Evaluation Demo file | Agilex™ F-series Arria® 10 SX |
ZCU106 | |
![]() AES-256 IP |
Datasheet | Rev1.02 | Rev1.03 |
Reference Design Document | Rev1.02 | Rev1.02 | |
Demo Instruction | Rev1.02 | Rev1.02 | |
Free Evaluation Demo file | Agilex™ F-series Arria® 10 SX |
ZCU106 | |
![]() AES-128 IP |
Datasheet | Rev1.02 | Rev1.02 |
Reference Design Document | Rev1.02 | Rev1.02 | |
Demo Instruction | Rev1.02 | Rev1.02 | |
Free Evaluation Demo file | Agilex™ F-series Arria® 10 SX |
ZCU106 |
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High throughput & Super Low Latency for secure communication applications.AES256-GCM IP core implement the advanced encryption standard (AES) with 256-bit key in Galois/Counter Mode (GCM) which is widely used for Authenticated Encryption with Associated Data (AEAD) application. This IP core can achieve high throughput 28.16Gbps @220MHz (AES256-GCM-10G25G IP), suitable to work together with Low Latency TOE10G IP core for high performance, low latency and secure communication applications. |
YouTube Video![]() AES256-GCM IP Introduction & Demo |
Features
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IP core | Document Name | Intel Agilex™/Arria® 10 |
Xilinx ZCU106 |
AES256-GCM 10G25G IP |
Datasheet | Rev1.02 | Rev1.03 |
Reference Design Document | Rev1.02 | Rev1.03 | |
Demo Instruction Document | Rev1.02 | Rev1.03 | |
Free Evaluation Demo file | Agilex™ F-series Arria® 10 SX |
ZCU106 | |
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AES256-GCM 1G IP |
Datasheet | Rev1.00 | |
Reference Design Document | Rev1.00 | ||
Demo Instruction Document | Rev1.00 | ||
Free Evaluation Demo file | ZCU106 |
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High throughput & Super Low Latency for secure storage applicationsAES256-XTS IP Core (AES256XTSIP) implement the advanced encryption standard (AES) with XEX Tweakable Block Cipher with Ciphertext Stealing (XTS) which is widely used in protecting the confidentiality of data on storage devices. |
YouTube Video![]() AES256-XTS IP Introduction & Demo |
Features
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IP core | Document Name | Intel Agilex™/Arria® 10 |
Xilinx ZCU106 |
AES256-XTS IP | Datasheet | Rev1.00 | Rev1.00 |
Reference Design Document | Rev1.00 | Rev1.00 | |
Demo Instruction Document | Rev1.00 | Rev1.00 | |
Free Evaluation Demo file | Agilex™ F-series Arria® 10 SX |
ZCU106 |