Application Specific IP Cores (AS-IP)Ultra high-speed and minimum latency
| Design Gateway Co., Ltd. provides Application Specific IP cores (AS-IP) based on rich experience from provider of high-speed Storage and Networking
IP Cores (Giga Bit IP cores). The AS-IP focus applications which require
high-speed and low latency such as finance and network equipments. |
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Low Latency Networking IP
 Design Gateway’s Low Latency (LL) Networking IP is designed from the ground
up for very low latency requirements. Especially, FinTech applications
such as high-frequency trading (HFT), high speed trading (HST), Market
Data Processing and Tick-to-Trade (T2T) systems. We can provide total solutions
for low latency Networking IP cores and FPGA logic customization for application
specific requirements. |
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| Intel | Xilinx |
| Learn more: LL Networking IP for Intel | Learn more: LL Networking IP for Xilinx |
| Presentation for Intel | Presentation for Xilinx |
Features
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Example Block diagram for Fintech application * Click to show more detail Design Gateway Provides optimized IP & Customized service for Fintech
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YouTube Video |
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 LL Networking IP introduction |
 TOE10GLL IP introduction |
Articles |
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tCAM IP
 tCAM-IP is a high performance, extremely low latency and highly configurable ternary
content-addressable memory IP. tCAM-IP can make deterministic search at
200MSPS continuously speed with constant latency at 7 clock cycles. It can achieve matching/filtering performance at 200,000,000 packets
per second over 40G/100G Ethernet. It is ideal for variant applications
such as network packet filtering/forwarding, intelligent switch/router,
deep packet inspection and network security application. We can provide
tCAM-IP custom reference design together with TOE40G/10G/1G-IP, UDP40G/10G/1G-IP, EMAC-IP based on customer requirements. Contact Us |
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| Intel | Xilinx |
| tCAM IP for Intel | tCAM IP for Xilinx |
| Presentation for Intel | |
YouTube Video |
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 tCAM-IP introduction |
 tCAM-IP performance demo on Arria 10 SX |
SHA-256 IP
SHA-256 IP is an optimized and efficient implementation of a secure hash algorithm SHA-256 specified in FIPS 180-4 standard. SHA256-IP can process 512-bit data blocks in just 65 clock cycles. Delivering 7.875Mbps throughput per 1MHz clock such as 1.575 Gbps throughput @ 200MHz. SHA-256 is one of the most secure and practically unbreakable hashing functions which is most popular to use in various applications such as secure password hashing, digital signature, SSL/TLS certificate and Bitcoin cryptocurrency. Together with Design Gateway's data storage and networking IP, SHA256-IP enables more opportunity for inventing the secure, efficient and high performance applications. |
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Features |
YouTube Video |
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 SHA-256 IP introduction |
Technical Documents |
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| Intel | Xilinx |
| Datasheet for Intel Rev1.00 | |
| Demo Instruction for Intel Rev1.00 | For Xilinx devices, please Contact Us |
| Evaluation Demo file for Arria 10 SX | |
AES-128 IP
AES-128 IP is 1st member of Advanced Encryption Standard (FIPS-197) IP Series, designed to support ECB mode for both encryption and decryption. AES128-IP computes 128-bit data blocks within constant 11 clock cycles. Delivering 11.6Mbps throughput per 1MHz clock such as 2.9 Gbps throughput @ 250MHz. AES Encryption IP Series is designed to enhance security features of existing Data Storage and Networking IP Cores. Enabling more opportunity for inventing the secure, efficient and high performance applications. |
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Features |
YouTube Video |
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 AES-128 IP Introduction |
Technical Documents |
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| Intel | Xilinx |
| Datasheet Rev1.00 | |
| Reference Design Document Rev1.00 | For Xilinx devices, please Contact Us |
| Demo Instruction Rev1.00 | |
| Evaluation Demo file for Arria 10 SX | |
Alliance Partner
Design Gateway Co., Ltd.
Head Office
3-23-17 Naka-cho, Koganei, Tokyo, JAPAN
R&D
89/13 Amornpan 205 Tower1, 11th floor, Ratchadapisek7 (Nathong) Alley, Ratchadapisek Road, Din Daeng, Bangkok, 10400 THAILAND