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The Expert of IP Core & Embedded


Application Specific IP Cores (AS-IP)Ultra high-speed and minimum latency

Design Gateway Co., Ltd. provides Application Specific IP cores (AS-IP) based on rich experience from provider of high-speed Storage and Networking IP Cores (Giga Bit IP cores). The AS-IP focus applications which require high-speed and low latency such as finance and network equipments.

  • Ultra High-speed and Low latency
  • Support the latest FPGAs
  • Provide flexible customization matched with system requirements. Contact Us
Low Latency Networking IPtCAM IPSHA-256 IPAES-128/256 IPAES256-GCM-10G IP

Low Latency Networking IP

Design Gateway’s Low Latency (LL) Networking IP is designed from the ground up for very low latency requirements. Especially, FinTech applications such as high-frequency trading (HFT), high speed trading (HST), Market Data Processing and Tick-to-Trade (T2T) systems. We can provide total solutions for low latency Networking IP cores and FPGA logic customization for application specific requirements.
Intel Xilinx
Learn more: LL Networking IP for Intel Learn more: LL Networking IP for Xilinx
Presentation for Intel Presentation for Xilinx
Turnkey Accelerator System

Key Features

  • Total super low latency solutions: EMAC, UDP and TOE
  • Available reference design on Accelerator Card
  • 100% CPU offload, and no external memory required
  • EMAC round trip latency ~70ns
  • 16 sessions UDP market data receiving latency ~99s (from EMAC to Application clock domain)
  • Suitable for FinTech applications
    • High-frequency trading (HFT)
    • Tick-to-Trade (T2T) systems
    • Market Data Processing

Accelerated High Frequency Trading (HFT) reference design


* Click to show more detail


We provides super low latency IPs and customized service for Fintech

YouTube Video


LL Networking IP introduction

TOE10GLL-IP
32 Session Demo

LL UDP10GRx-IP
16 Session Demo

LL 10G EMAC-IP
with Xilinx’s AATDemo

Articles


tCAM IP

tCAM-IP is a high performance, extremely low latency and highly configurable ternary content-addressable memory IP. tCAM-IP can make deterministic search at 200MSPS continuously speed with constant latency at 7 clock cycles. It can achieve matching/filtering performance at 200,000,000 packets per second over 40G/100G Ethernet. It is ideal for variant applications such as network packet filtering/forwarding, intelligent switch/router, deep packet inspection and network security application. We can provide tCAM-IP custom reference design together with TOE40G/10G/1G-IP, UDP40G/10G/1G-IP, EMAC-IP based on customer requirements. Contact Us
Intel Xilinx
tCAM IP for Intel tCAM IP for Xilinx

YouTube Video


tCAM-IP introduction

tCAM-IP performance demo on Arria 10 SX

tCAM-IP performance demo on Arria 10 SX

Blog: What's TCAM?

SHA-256 IP

 

SHA-256 IP is an optimized and efficient implementation of a secure hash algorithm SHA-256 specified in FIPS 180-4 standard. SHA256-IP can process 512-bit data blocks in just 65 clock cycles. Delivering 7.875Mbps throughput per 1MHz clock such as 2.362 Gbps throughput @ 300MHz. * tentative

SHA-256 is one of the most secure and practically unbreakable hashing functions which is most popular to use in various applications such as secure password hashing, digital signature, SSL/TLS certificate and Bitcoin cryptocurrency.

Together with Design Gateway's data storage and networking IP, SHA256-IP enables more opportunity for inventing the secure, efficient and high performance applications.

 

Features

YouTube Video

  • Support SHA 256-bit standard function
  • Support input data length up to 261-1 bytes (264-8 bits)
  • Super high throughput rate at 65 clocks per 64 bytes data
  • Hash speed up to 2.362 Gbps @ 300MHz * tentative
  • Simple user interface signals as same as FIFO interface
  • Small Resource Consumption

SHA-256 IP introduction

Technical Documents

Intel Xilinx
Datasheet for Intel Rev1.00
Demo Instruction for Intel Rev1.00 For Xilinx devices, please Contact Us
Evaluation Demo file for Arria 10 SX

AES-128/256 IP

  

AES-128 IP is 1st member of Advanced Encryption Standard (FIPS-197) IP Series, designed to support ECB mode for both encryption and decryption. AES128-IP computes 128-bit data blocks within constant 11 clock cycles. Delivering 11.6Mbps throughput per 1MHz such as 5.8 Gbps @ 500MHz.

AES-256SS IP specializes in ultra-high throughput and ultra-low latency. IP computes 128-bit data blocks within constant 1 clock cycle. Delivering 128Mbps throughput per 1MHz such as 51.2 Gbps @ 400MHz.

AES Encryption IP Series is designed to enhance security features of existing Data Storage and Networking IP Cores. Enabling more opportunity for inventing the secure, efficient and high performance applications.

Features

YouTube Video

  • Support AES ECB mode standard.
  • Key size
    • AES-128 IP: 128 bit
    • AES-256 IP: 256 bit
  • Support input data width128-bit.
  • High-Throughput rate
    • AES-256SS IP: 51.2 Gbps @400MHz, 128 Mbits/MHz
    • AES-128 IP: 5.8 Gbps @500MHz, 11.6 Mbits/MHz
    • AES-256 IP: 4.26 Gbps @500MHz, 8.53 Mbits/MHz
  • Low Latency
    • AES-256SS IP: 1 clock cycles for 128-bit data calculation
    • AES-128 IP: 11 clock cycles for 128-bit data calculation
    • AES-256 IP: 15 clock cycles for 128-bit data calculation

AES-128 IP Introduction

Technical Documents

IP core Document Name Intel
Arria® 10 SX
Xilinx
ZCU106

AES-256SS IP
Datasheet Rev1.02
Reference Design Document Rev1.02
Demo Instruction Rev1.02
Free Evaluation Demo file ZCU106

AES-256 IP
Datasheet Rev1.00 Rev1.02
Reference Design Document Rev1.00 Rev1.02
Demo Instruction Rev1.00 Rev1.02
Free Evaluation Demo file Arria® 10 SX ZCU106

AES-128 IP
Datasheet Rev1.01 Rev1.02
Reference Design Document Rev1.01 Rev1.02
Demo Instruction Rev1.01 Rev1.02
Free Evaluation Demo file Arria® 10 SX ZCU106

AES256-GCM IP

High throughput 19.2Gbps @300MHz AES GCM IP Core for secure communication applications.

AES256-GCM-10G/1G IP core implement the advanced encryption standard (AES) with 256-bit key in Galois/Counter Mode (GCM) which is widely used for Authenticated Encryption with Associated Data (AEAD) application. This IP core can achieve high throughput 19.2Gbps @300MHz, suitable to work together with Low Latency TOE10G IP core for high performance, low latency and secure communication applications.

YouTube Video


AES256-GCM IP Introduction & Demo

Features

  • Support AES-GCM mode standard.
  • Support 256-bit key size, 96-bit iv size.
  • Support zero-length AAD or data input.
  • Peak throughput rate at 64 Mbits/MHz.
  • High-throughput
    • AES256-GCM10G IP Speed up to 19.2 Gbps @300MHz
    • AES256-GCM1G IP Speed up to 3.2 Gbps @350MHz

Technical Documents

IP core Document Name Intel Xilinx
ZCU106

AES256-GCM-10G IP
Datasheet Rev1.00
Reference Design Document Rev1.00
Demo Instruction Document Rev1.00
Free Evaluation Demo file ZCU106


AES256-GCM-1G IP
Datasheet Rev1.00
Reference Design Document Rev1.00
Demo Instruction Document Rev1.00
Free Evaluation Demo file ZCU106


Alliance Partner




Design Gateway Co., Ltd.

Head Office
3-23-17 Naka-cho, Koganei, Tokyo, JAPAN
R&D
89/13 Amornpan 205 Tower1, 11th floor, Ratchadapisek7 (Nathong) Alley, Ratchadapisek Road, Din Daeng, Bangkok, 10400 THAILAND