Design Gateway provides security IP cores and search IP core that are highly compatible with DG's ultra-high-speed storage and network IP cores. By implementing highly reliable security features for ultra-high-speed data transfer, it becomes possible to develop even higher value-added applications.
for Mission-critical Applications | for Secure Storage Application |
for Secure Network Application |
High throughput Encryption IP | High throughput Security IP | 200M SPS Search Engine |
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Introduction VideoSecurity IPs Introduction Video ![]() Blogs [Security] ![]() |
Features of Security IPs
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Product Brochuresfor AMD (Rev2.6EX) | for Altera (Rev2023Q4)Technical UpdatesTechnical & Marketing Document Updates |
Security IP core series Design Guide |
![]() for Altera | for AMD |
TLS1.3 IP (Transport Layer Security IP) is the CPU-less & High-performance TLS v1.3 protocol engine for FPGA Acceleration with no CPU and external memory required. Providing maximum Gigabit Ethernet throughput for highly secure data transmission over 1G/10G/25G/100G network. Protect your valuable data from potential security breaches by using TLS secure transmission now! Especially, in Industrial IoT & Automation, Aerospace & Defense Applications. Our TLS 1.3 IP core demo can successfully demonstrate very high throughput HTTPS Upload and Download with standard web server by pure hardware logic on FPGA. |
YouTube Video![]() TLS1.3 Server 10G IP Introduction & Performance Demo |
Key Features
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High throughput & Super Low Latency for secure storage applicationsAES256-XTS IP Core (AES256XTSIP) implement the advanced encryption standard (AES) with XEX Tweakable Block Cipher with Ciphertext Stealing (XTS) which is widely used in protecting the confidentiality of data on storage devices. |
YouTube Video![]() AES256-XTS IP Introduction & Demo |
Features
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Document Name | Altera | AMD |
Datasheet | Rev1.01 | Rev1.01 |
Reference Design Document | Rev1.00 | Rev1.00 |
AES-IP core series Design Guide | Rev1.00 | Rev1.00 |
Demo Instruction Document | Rev1.00 | Rev1.00 |
Free Evaluation Demo file | Agilex™ F-series Arria® 10 SX |
ZCU106 |
AES256-XTS-STG IP implement the advanced encryption standard (AES) with XEX (XOR Encrypt XOR) tweakable block cipher which operates sequences of complete blocks and is widely used in protecting the confidentiality of data on various storage devices with interfaces such as NVMe and SATA. We also have a lineup of "2X" ideal for NVMe PCIe Gen4, and "4X", supported Gen5. |
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Features
YouTube Video![]() Enhancing NVMe SSD Security with AES256-XTS-STG Encryption |
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Document Name | Altera | AMD |
AES256-XTS-STG IP Datasheet | Rev1.00 | Rev1.01 |
AES256-XTS-STG IP Reference Design Document |
Rev1.00 | Rev1.00 |
AES256-XTS-STG IP with NVMe-IP Reference Design Document |
Rev1.01 | Rev1.03 |
Demo Instruction Document | Rev1.00 | Rev1.01 |
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Free Evaluation Demo file | ||
AES256-XTS-STG IP (for NVMe Gen3) | Arria® 10 SX | |
AES256-XTS-STG-2X IP (for NVMe Gen4) | VCK190 | |
AES256-XTS-STG-4X IP (for NVMe Gen5) | Agilex™ I-series | VPK120 |
AES256-XTS-STG IP (with NVMe Gen3 IP) | Arria® 10 SX | |
AES256-XTS-STG-2X IP (with NVMe Gen4 IP) | VCK190 | |
AES256-XTS-STG-4X IP (with NVMe Gen5 IP) | Agilex™ I-series | VHK158 |
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Free Evaluation Project | ||
AES256-XTS-STG IP (for NVMe Gen3) | Github ![]() |
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AES256-XTS-STG-2X IP (for NVMe Gen4) | Github ![]() |
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AES256-XTS-STG-4X IP (for NVMe Gen5) | Github ![]() |
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High throughput & Super Low Latency for secure communication applications.AES256-GCM IP core implement the advanced encryption standard (AES) with 256-bit key in Galois/Counter Mode (GCM) which is widely used for Authenticated Encryption with Associated Data (AEAD) application. This IP is suitable to work together with Low Latency TOE10G IP core for high performance, low latency and secure communication applications. |
YouTube Video![]() AES256-GCM100G IP Introduction & Demo |
Features
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IP core | Document Name | Altera | AMD |
AES256-GCM 100G IP |
Datasheet | Rev1.00 | Rev1.00 |
Reference Design Document | Rev1.00 | Rev1.00 | |
Demo Instruction Document | Rev1.00 | Rev1.01 | |
Free Evaluation Demo file | Agilex™ F-series Arria® 10 SX |
ZCU106 KCU116 |
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Free Evaluation Project | Github ![]() |
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AES256-GCM 10G25G IP |
Datasheet | Rev2.01 | Rev2.01 |
Reference Design Document | Rev2.01 | Rev2.01 | |
Demo Instruction Document | Rev2.01 | Rev2.01 Rev1.00 (KR260) |
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Free Evaluation Demo file | Agilex™ F-series Arria® 10 SX |
KCU116 ZCU106 KR260 |
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Free Evaluation Project | Github ![]() |
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AES256-GCM 1G IP |
Datasheet | Rev1.00 | |
Reference Design Document | Rev1.00 | ||
Demo Instruction Document | Rev1.00 | ||
Free Evaluation Demo file | ZCU106 | ||
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Common | AES-IP core series Design Guide | Rev1.00 |
![]() AES-256SS IP specializes in ultra-high throughput and ultra-low latency. IP computes 128-bit data blocks in every 1 clock cycle. Delivering 128Mbps throughput per 1MHz such as 51.2 Gbps @ 400MHz. ![]() AES-128 IP is 1st member of Advanced Encryption Standard (FIPS-197) IP Series, designed to support ECB mode for both encryption and decryption. AES128-IP computes 128-bit data blocks within constant 11 clock cycles. Delivering 11.6Mbps throughput per 1MHz such as 5.8 Gbps @ 500MHz. AES Encryption IP Series is designed to enhance security features of existing Data Storage and Networking IP Cores. Enabling more opportunity for inventing the secure, efficient and high performance applications. |
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Features |
YouTube Video |
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![]() AES-128 IP Introduction |
IP core | Document Name | Altera | AMD |
![]() AES-256SS IP |
Datasheet | Rev1.03 | Rev1.04 |
Reference Design Document | Rev1.02 | Rev1.02 | |
Demo Instruction | Rev1.02 | Rev1.02 | |
Free Evaluation Demo file | Agilex™ F-series Arria® 10 SX |
ZCU106 | |
![]() AES-256 IP |
Datasheet | Rev1.03 | Rev1.04 |
Reference Design Document | Rev1.03 | Rev1.02 | |
Demo Instruction | Rev1.03 | Rev1.02 | |
Free Evaluation Demo file | Agilex™ F-series Arria® 10 SX |
ZCU106 | |
![]() AES-128 IP |
Datasheet | Rev1.03 | Rev1.03 |
Reference Design Document | Rev1.03 | Rev1.03 | |
Demo Instruction | Rev1.02 | Rev1.02 | |
Free Evaluation Demo file | Agilex™ F-series Arria® 10 SX |
ZCU106 | |
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Common | AES-IP core series Design Guide | Rev1.00 |
The SHA2 IP Core supports SHA-224, SHA-256, SHA-384, SHA-512, SHA-512/224, and SHA-512/256 secure hash algorithms. The core is fully compliant with the FIPS PUB 180-4 (Federal Information Processing Standard) specification. Suitable for applications such as secure communication, password authentication, and blockchain data integrity.
Features |
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Technical Documents |
Document Name | Altera | AMD |
Datasheet | Rev1.00 | Rev1.00 |
Referrence Design Document | Rev1.00 | Rev1.00 |
Demo Instruction | Rev1.00 | Rev1.00 |
Evaluation Demo file | Agilex 7 I-series Arria 10 SX |
KCU116 |
SHA-256 IP is an optimized and efficient implementation of a secure hash algorithm SHA-256 specified in FIPS 180-4 standard. SHA256-IP can process 512-bit data blocks in just 65 clock cycles. Delivering 7.875Mbps throughput per 1MHz clock such as 2.362 Gbps throughput @ 300MHz. * tentative
SHA-256 is one of the most secure and practically unbreakable hashing functions which is most popular to use in various applications such as secure password hashing, digital signature, SSL/TLS certificate and Bitcoin cryptocurrency.
Together with Design Gateway's data storage and networking IP, SHA256-IP enables more opportunity for inventing the secure, efficient and high performance applications.
Features |
YouTube Video |
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![]() SHA-256 IP introduction |
Technical Documents |
Document Name | Altera | AMD |
Datasheet | Rev1.00 | Rev1.00 |
Demo Instruction | Rev1.00 | Rev1.00 |
Evaluation Demo file | Arria 10 SX | KCU105 |
![]() tCAM-IP is a high performance, extremely low latency and highly configurable ternary content-addressable memory IP. tCAM-IP can make deterministic search at 300MSPS continuously speed with constant latency at 7 clock cycles. It can achieve matching/filtering performance at 300,000,000 packets per second over 40G/100G Ethernet. It is ideal for variant applications such as network packet filtering/forwarding, intelligent switch/router, deep packet inspection and network security application. We can provide tCAM-IP custom reference design together with TOE40G/10G/1G-IP, UDP40G/10G/1G-IP, EMAC-IP based on customer requirements. Contact Us |
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Altera | AMD | ||
tCAM IP for Altera | tCAM IP for AMD | ||
YouTube Video |
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![]() UDP Packet Filtering & Switching Demo |
![]() tCAM-IP introduction |
![]() tCAM-IP performance demo on Arria 10 SX |
![]() tCAM-IP performance demo on KCU116 |