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1 Introduction 2 Hardware Overview 2.1 AsyncAxiReg 2.2 UserReg 2.3 Ethernet Subsystem. 2.3.1 DG LL10GEMAC-IP 2.3.2 10G/25G Ethernet Subsystem. 3 CPU Firmware 3.1 Set Gateway IP Address 3.2 Set FPGA IP Address 3.3 Set FPGA MAC address 3.4 Load network parameters 3.5 Set FPGA Port Number 3.6 Show key materials 3.7 Show certificate information 3.8 Show session parameters 3.9 Download data pattern with HTTP GET command 3.10 Upload data pattern with HTTP POST command. 17 Upload data pattern with HTTP POST command 3.11 Upload and Download data pattern like secnetperf 18 Upload and Download data pattern like secnetperf 4 Revision History Return to Top

QUIC10GC-IP Reference Design