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1 Introduction 2 Hardware Overview 2.1 AsyncAXIReg 2.2 UserReg 3 Hardware Operation Sequences 3.1 Operation Overview 3.2 Parameter Setting 3.3 Hash with Message from User 3.4 Hash Performance Test Mode with Constant Input 3.5 Hash Output 4 CPU Firmware Logic 4.1 Hash with Input Message 4.2 Hash performance test mode 4.3 SHA3 Variant Selection 5 Revision History Return to Top

SHA3-IP Reference Design

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