Features Applications General Description Functional Description Control Block Parameter Registers (Param Regs) UDP/IP Engine Transmit Block Tx Data Buffer Tx Packet Buffer Packet Builder Receive Block Rx Packet Buffer Packet Filtering Rx Data Buffer User Block Ethernet Subsystem (10G/25G Base-R) DG 10G25GEMAC IP DG 25GEMAC/PCS + RS-FEC IP AMD 10G/25G Ethernet Subsystem (Soft IP) The Versal Multirate Ethernet MAC Subsystem (Hard IP) Core I/O Signals Timing Diagram. IP Reset IP Initialization Data Transmission Data Reception Interrupt Ethernet MAC Interface Verification Methods Recommended Design Experience Ordering Information Revision History Return to Top