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High-frequency trading on AMD Alveo

Accelerated Algorithmic Trading (AAT)

Accelerate High-Frequency Trading with an ultra-low-latency stack on FPGA powered by Design Gateway Low-Latency IP. The system receives real-time market data via UDP, processes it through a configurable pricing engine (deployable on-card or in host software), and executes orders via TCP, all while maintaining sub-microsecond latency. AAT offers a purpose-built architecture with deterministic Ethernet/TCP/UDP paths and flexible pricing-engine deployment to reduce latency and shorten time-to-market. Choose the flow that fits your team— Vitis, QDMA, or Calypte —and scale from prototype to production.

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10G EthernetPCIe DMASub-µs focusOn-card / Host pricing
Market data: UDPOrders: TCPMin. 2×10G links

Why AAT with Design Gateway

Market-proven Low-Latency IP

DG Low-Latency IP suite (LL10GEMAC-IP, UDP10GRx, and TOE10GLL) provide deterministic Ethernet/TCP/UDP paths optimized for exchange traffic.

Multiple deployment options

Offers multiple deployment designs — Vitis, QDMA, or Calypte — tailored to your latency targets and pricing-engine placement.

Reference designs & docs

Complete reference designs for each deployment option, accompanied by comprehensive documentation that clarifies the system and prepares you to integrate the pricing engine—whether on‑card or in host software.

Ultra-Low Latency Trading with FPGA Acceleration

Comparison diagram — click to enlarge

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AAT Solution Overview

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Architecture — Block diagram

Accelerated Algorithmic Trading (AAT) Host System (Trader) Target System (Stock Market) CPU HW Config/ Control/Monitor DMA Driver PCIe FPGA DMA Engine Trading Engine (HLS) -User Module- Ethernet Subsystem 10GbE Market

Interactive block diagram — hover or tap the blocks for short descriptions.

Quick summary

Select flows to filter the comparison below. Leave all unselected to compare everything.

What’s inside AAT

Networking IP (DG)

Ultra-low-latency Ethernet & transport.

LL10GEMAC-IP UDP10GRx TOE10GLL
Docs & downloads

DMA & Host stack

Choose the PCIe/host flow that fits your ops.

XDMA + XRT QDMA + QDMA DPDK Driver Calypte + NFB Driver

Target platforms

Deploy on AMD Alveo.

X3522 U50 U250 U55C Others on request

Deliverables & support

Reference design

Complete FPGA hardware projects with pre-integrated DG Low-Latency IP cores, ready-to-build Vivado/Vitis projects, and example trading applications for supported Alveo platforms.

Documentation

Complete guides for system understanding and each flow with architecture details, build/run instructions.

Engineering support

Engage with DG engineers for integration, validation, and optimization best practices. For any questions or customization requirements, please contact us.

FAQ

Can the pricing engine run on the card?

Yes. Designs can place the pricing engine on-card (for lower latency by eliminating PCIe round-trips) or in host software (for flexibility and easier updates) depending on your specification or strategy requirements.

What protocols are supported?

Our design supports the FIX protocol (CME) and ITCH/OUCH (NASDAQ), with the system using UDP for market data reception and TCP for order execution. For different protocols or customized integrations, please contact us to discuss your specific requirements.

Success Stories

Thailand SET Market

Design Gateway partnered with Vanta to deploy Alveo-based low-latency trading for the SET, delivering a production-proven system with validated market-data and order pipeline currently in live operation.

Market: SET Protocol: ITCH/OUCH Board: U50 On-card & Host options