The Expert of IP Core & Embedded

Design Gateway’s Low Latency Networking IP is designed from the ground up for very low latency requirements. Especially, FinTech applications such as high-frequency trading (HFT), high speed trading (HST), Market Data Processing and Tick-to-Trade (T2T) systems. We can provide total solutions for low latency Networking IP cores and FPGA logic customization for application specific requirements. Contact Us

Accelerated High Frequency Trading (HFT) reference design

DG's Low latency IP demo together with Xilinx's open-source reference design, Accelerated Algorithmic Trading (AAT) is now available on Alveo U50 and U250 Card. Turnkey Accelerator system

• LL10GEMAC-IP demo with Xilinx ‘s AAT (click for demo)
  More than 100ns latency reduction and functional compatible with Xilinx’s AAT
• LL10GEMAC-IP & UDP10GRx-IP demo with Xilinx AAT (click for demo)
  Together with 16 sessions low latency UDP IP, 100% UDP protocol handling by IP core.

Features

Low Latency 10GEMAC-IP (LL10GEMAC-IP)

10 Gbps Ethernet MAC and PCS Directly connecting with 32-bit PMA by Xilinx IP wizard Low latency: 65.1 ns for round-trip latency 18.6 ns for Tx path, 21.7 ns for Rx path, 24.8 ns for PMA latency Small resource utilization Minimum Tx packet size: 5 bytes FCS (CRC-32) inserting and checking Individual clock domain for transmit and receive interface at 322.265625 MHz Reference design available on Xilinx FPGA boards AAT demo available on Xilinx Alveo cards

DG LL 10G EMAC-IP with Xilinx’s AAT demo

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Low Latency UDP10G Rx/Tx-IP

All Hard wired Logic, CPU less and no external memory required Operation mode: Unicast or Multicast (IGMPv3) Support Multi-session up to 4 sessions (More sessions can be customized) Configuration mode: Master or Slave (for multiple IP connecting) Direct connect with super low latency DG 10GbE MAC core (LL10GEMAC-IP) HDL design for minimized resource and latency RX Latency: 37.2 ns (@ 322.266MHz) Available reference design: 4 and 16 sessions demo

DG LL UDP10GRx-IP 16 Sessions demo for FinTech

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Low Latency TOE10G-IP (TOE10GLL-IP)

All Hard wired Logic, CPU less and no external memory required Configured by two data transmission mode: Simple mode & Cut-through mode Support 1 sessions (More sessions can be customized) Support ICMP Echo reply (Ping): Up to 118-byte payload data Direct connect with super low latency DG 10GbE MAC core (LL10GEMAC-IP) HDL design for minimized resource and latency Low Latency: (@ 322.265625 MHz) RX Latency: 46.5 ns TX Latency: 6.2 ns Available reference design: 1 and 32 sessions demo

DG TOE10GLL-IP 32 Sessions demo

Document download

Document name	Update (Revision)
Presentation	1.0E
Brochure	2.6EX

IP core & Option	Datasheet	Reference Design Document	Demo Instruction Document	FPGA Board Setup	Free Evaluation demo file Contact Us
LL 10GEMAC-IP	Rev1.1	Rev1.0	Rev1.1	Rev1.0	ZCU102
Accelerated Algorithmic Trading (AAT) Demo		Rev1.0	Rev1.1		U50 U250
LL UDP10GRx-IP	Rev2.0	Rev1.2	Rev1.2	Rev1.1	ZCU102 KCU116
16 Session Demo		Rev1.0	Rev1.0		ZCU102 KCU116
TOE10GLL-IP	Rev1.2	Rev1.2	Rev1.2		ZCU102 ZCU106
32 Session Demo		Rev1.0	Rev1.0		ZCU102 ZCU106
Accelerated Algorithmic Trading (AAT) Demo		Rev2.0	Rev1.1		U50 U250

For more detail, please Contact Us