Supercharge your trading strategies with the Accelerated Algorithmic Trading (AAT) Accelerator & System — a cutting-edge turnkey solution engineered to meet the relentless demands of today's financial markets. Powered by FPGA acceleration and ultra-low-latency IP core technology, the AAT System is the ultimate tool for Brokers, Exchanges, Market Data Vendors, Sell-Side Vendors, and Proprietary Traders seeking a definitive competitive edge.
DG's Low latency IP Cores (TOE, UDP and EMAC) demo together with Accelerated Algorithmic Trading (AAT) reference design based on HLS(C/C++) example code is now available on Alveo X3552PV Card and also standard alone AMD FPGA Boards.click for demo
The Accelerated Algorithmic Trading with QDMA (AAT-QDMA) demo is the latest reference design demonstrates a high-performance trading system over 10G Ethernet based on best in class cost effective and super low latency, Alveo X3552PV Card and HLS(C/C++) based reference design for High Frequency Trading application by FPGA hardware. More detail
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![]() ![]() DG LL 10G EMAC-IP + AAT QDMA Demo ![]() |
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![]() ![]() DG LL UDP10GRx-IP 16 Sessions demo for FinTech ![]() |
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![]() ![]() DG TOE10GLL-IP 32 Sessions demo ![]() |
Document name | Update (Revision) |
Presentation | 1.0E |
Brochure | 2.6EX |
IP core & Option | Datasheet | Reference Design Document | Demo Instruction Document | FPGA Board Setup | Free Evaluation demo file | ![]() |
Accelerated Algorithmic Trading (AAT) Demo |
Rev2.0 | Rev1.1 | U50 U250 |
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LL 10GEMAC-IP | Rev1.04 | Rev1.1 | Rev1.1 | Rev1.0 | ZCU102 | |
Accelerated Algorithmic Trading (AAT) QDMA Demo |
Rev1.00 | Rev1.01 | X3522 U50 U55C U250 |
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Accelerated Algorithmic Trading (AAT) Demo |
Rev1.1 | Rev1.03 | U50 U250 |
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LL UDP10GRx-IP | Rev2.0 | Rev1.2 | Rev1.2 | Rev1.1 | ZCU102 KCU116 |
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16 Session Demo | Rev1.0 | Rev1.0 | ZCU102 KCU116 |
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TOE10GLL-IP | Rev2.0 | Rev1.2 | Rev1.1 | ZCU102 ZCU106 |
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32 Session Demo | Rev1.0 | Rev1.0 | ZCU102 ZCU106 |
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