本文へスキップ

The Expert of IP Core & Embedded

|

Super Low Latency Networking IPfor fintech

LL10GEMAC IP┃LLUDP10G IP┃LLTOE10G IP┃Document Download
Design Gateway’s Low Latency Networking IP is designed from the ground up for very low latency requirements. Especially, FinTech applications such as high-frequency trading (HFT), high speed trading (HST), Market Data Processing and Tick-to-Trade (T2T) systems. We can provide total solutions for low latency Networking IP cores and FPGA logic customization for application specific requirements. Contact Us

Accelerated High Frequency Trading (HFT) reference design



DG's Low latency IP demo together with AMD's open-source reference design, Accelerated Algorithmic Trading (AAT) is now available on Alveo U50 and U250 Card. click for demo

Breaking Latency Barriers in Stock Trading with AMD AAT and DG Low-Latency IP cores
Blog Article
The Enhanced AMD's Stock Trading (AAT) demo by integrating DG's Low-Latency IP cores
Blog Article

Features

Low Latency 10GEMAC-IP (LL10GEMAC-IP)

  • 10 Gbps Ethernet MAC and PCS
  • Directly connecting with 32-bit PMA by AMD IP wizard
  • Low latency: 65.1 ns for round-trip latency
    18.6 ns for Tx path, 21.7 ns for Rx path,
    24.8 ns for PMA latency
  • Small resource utilization
  • Minimum Tx packet size: 5 bytes
  • FCS (CRC-32) inserting and checking
  • Individual clock domain for transmit and receive interface at 322.265625 MHz
  • Reference design available on AMD FPGA boards
  • AAT demo available on AMD Alveo cards

DG LL 10G EMAC-IP with AMD’s AAT demo

Low Latency UDP10G Rx/Tx-IP

  • All Hard wired Logic, CPU less and no external memory required
  • Operation mode: Unicast or Multicast (IGMPv3)
  • Support Multi-session up to 4 sessions
    (More sessions can be customized)
  • Configuration mode: Master or Slave
    (for multiple IP connecting)
  • Direct connect with super low latency DG 10GbE MAC core (LL10GEMAC-IP)
  • HDL design for minimized resource and latency
  • RX Latency: 37.2 ns (@ 322.266MHz)
  • Available reference design: 4 and 16 sessions demo

DG LL UDP10GRx-IP 16 Sessions demo for FinTech

Low Latency TOE10G-IP (TOE10GLL-IP)

  • All Hard wired Logic, CPU less and no external memory required
  • Configured by two data transmission mode:
    Simple mode & Cut-through mode
  • Support 1 sessions (More sessions can be customized)
  • Support ICMP Echo reply (Ping): Up to 118-byte payload data
  • Direct connect with super low latency DG 10GbE MAC core (LL10GEMAC-IP)
  • HDL design for minimized resource and latency
  • Low Latency: (@ 322.265625 MHz)
    • RX Latency: 46.5 ns
    • TX Latency: 6.2 ns
  • Available reference design: 1 and 32 sessions demo

DG TOE10GLL-IP 32 Sessions demo

Document download

Document name Update (Revision)
Presentation 1.0E
Brochure 2.6EX
IP core & Option Datasheet Reference Design Document Demo Instruction Document FPGA Board Setup Free Evaluation demo file
Accelerated Algorithmic Trading
(AAT) Demo		 Rev2.0 Rev1.1 U50
U250
LL 10GEMAC-IP Rev1.03 Rev1.1 Rev1.1 Rev1.0 ZCU102
Accelerated Algorithmic Trading
(AAT) Demo		 Rev1.1 Rev1.03 U50
U250
LL UDP10GRx-IP Rev2.0 Rev1.2 Rev1.2 Rev1.1 ZCU102
KCU116
16 Session Demo Rev1.0 Rev1.0 ZCU102
KCU116
TOE10GLL-IP Rev2.0 Rev1.2 Rev1.1 ZCU102
ZCU106
32 Session Demo Rev1.0 Rev1.0 ZCU102
ZCU106

For more detail, please Contact Us



Alliance Partner


Design Gateway Co., Ltd.

Head Office
3-23-17 Naka-cho, Koganei, Tokyo, JAPAN
R&D
89/26 Amornpan 205 Tower1, 18th floor, Ratchadapisek7 (Nathong) Alley, Ratchadapisek Road, Din Daeng, Bangkok, 10400 THAILAND

AI Lab
Faculty of Engineering, Chulalongkorn University, 12th floor, Engineering 4 Building (Charoenvidsavakham), Phayathai Rd., Wang Mai, Pathumwan, Bangkok, 10330 THAILAND