DesignGateway Co., Ltd. The Expert of IP Core

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The latest Technical Documents Update here

Sep 18, 2024

Design Gateway collaborates with the Multimedia Data Analytics and Processing Research Unit (MDAP) of the Faculty of Engineering, Chulalongkorn University to launch a lab to develop AI IP cores for FPGA and ASIC. Read more (LinkedIn) | Read more (Facebook, Thai)

Learn more about MDAP, Chulalongkorn University

Sep 2024

On September 26th, Design Gateway will hold the FPGA Edge AI Professional Workshop using AMD Kria KV260 at Burapha University Eastern Science and Technology Park (EaST), Thailand.
Learn more (Thai)

Jul 2024 [ NEW PRODUCT RELEASE ]

QUIC IP core is released.
Learn more for Altera | Learn more for AMD

Jun 2024 [ NEW PRODUCT RELEASE ]

TOE200GADV IP core is released.
Learn more for Altera | Learn more for AMD

Feb 2024 [ NEW PRODUCT RELEASE ]

TOE100GADV IP core is released.
Learn more for Altera | Learn more for AMD

Dec 7, 2023

FPGA-Based Accelerator Systems Proven to Deliver Ultra-Fast Trading Capabilities at The Stock Exchange of Thailand (SET)
Learn more about Low Latency Networking IP cores

Jul 7, 2023 [ NEW PRODUCT RELEASE ]

TLS1.3 IP (Transport Layer Security IP) is the CPU-less & High-performance TLS v1.3 protocol engine for FPGA Acceleration with no CPU and external memory required. Providing maximum Gigabit Ethernet throughput for highly secure data transmission over 1G/10G/25G/100G network. Protect your valuable data from potential security breaches by using TLS secure transmission now! Especially, in Industrial IoT & Automation, Aerospace & Defense Applications.
Learn more about TLS1.3 IP core

May 6, 2023 [ NEW PRODUCT RELEASE ]

NVMe IP, a PCIe Gen5 next-generation NVMe host controller for Altera (Intel) Agilex™ 7 FPGA, is now available.

Learn more about NVMe Gen5 IP core for Altera (Intel) Agilex™ 7 FPGA

NVMe Gen5 IP Introduction & Demo Video

AB19-M2PCI is released for NVMe Gen5 IP evaluation with Altera (Intel) Agilex™ 7 FPGA I-series development kit.Purchase from Mouser

AB19-M2PCI

Apr 6, 2023 [ NEW PRODUCT RELEASE ]

AES256-GCM100G IP Core is designed to meet NIST standards with high performance throughput over 100Gbps. It's suitable TLS and SSL offload and acceleration by FPGA for any application that required 100G throughput over secure network communication.
Learn more about AES256-GCM100G IP

Mar 1, 2023

Design Gateway has been selected to join Silicom Denmark’s PARTNER IP program. Enabling Design Gateway and Silicom Denmark customers to easily get access to the demo, reference design and IP Cores in Networking, Data Storage and Security for Silicom’s FPGA-Based SmartNIC product. Learn more

Feb 14, 2023 [ NEW PRODUCT RELEASE ]

rmNVMe IP (Random Access & Multi User NVMe IP) is very high performance NVMe Host Controller which is highly optimized for high-IOPS random access applications. rmNVMe-IP supports multiple user interfaces, each user can simultaneously read/write to a single NVMe SSD at the same time. This IP is designed for the application that requires very high random access performance such as real-time sensors data fusion and processing, OS file systems offloading and NVMe SSD tester.
Learn more about rmNVMe IP for AMD│Learn more about rmNVMe IP for Altera (Intel)

Jan 17, 2023 [ NEW PRODUCT RELEASE ]

AES256-XTS IP core implement the advanced encryption standard (AES) with 256-bit key in Galois/Counter Mode (GCM) which is widely used for Authenticated Encryption with Associated Data (AEAD) application.
Learn more about AES256-XTS IP

Nov 8, 2022

Design Gateway in collaboration with the Faculty of Engineering, Khon Kaen University will hold the Digital Design with FPGA Camp (DD-Camp) at KKU Makerspace during 17-24 November 2022.

DD-Camp is the comprehensive Training Camp and design challenge for engineering students that will pave the way for digital engineering technology and open up the opportunity for the future development of Semiconductor and DeepTech industry in Thailand.

About Digital Design with FPGA Camp (DD-Camp)
About Engineering @KKU

Oct 18, 2022

Design Gateway joins Altera (Intel) FPGA Technology Day 2022 in Japan as Gold partner.
Date: Nov 15-18, 2021
Place: Online Event
Read More (Registration)

Aug 18, 2022 [ NEW PRODUCT RELEASE ]

AES256-GCM-10G/1G IP core implement the advanced encryption standard (AES) with 256-bit key in Galois/Counter Mode (GCM) which is widely used for Authenticated Encryption with Associated Data (AEAD) application.
Learn more about AES256-GCM-10G/1G IP

AES256GCM-IP Introduction & Performance demo

Jun 24, 2022 [ NEW PRODUCT RELEASE ]

muNVMe IP (Multi User NVMe IP) is pure hardware logic solutions for very high throughput, multiple data streaming access to NVMe SSD simultaneously without CPU. Simplify your system complexity and maximize performance.
Learn more about muNVMe IP for AMD│Learn more about muNVMe IP for Altera (Intel)

muNVMe-IP Introduction & Performance demo

May 10, 2022

The TOE100G-IP core multiple sessions reference design is implemented to utilize 100G Ethernet channel effectively and maximize TCP throughput by multiple instances of TOE100G-IP. It impro It significantly improves the performance of TCP communication dropped due to the restrictions on the PC side without any expensive enterprise grade server.
TOE100G-IP 4 session demo on YouTube

Learn more TOE-IP core series page (for AMD)

TOE100G-IP 4 session demo
on YouTube

Jan 5, 2022

Turnkey Accelerator system Demo Series are available on YouTube.

Product Introduction
[EP0]

System Setup & Validation
[EP1]

DG LL 10G EMAC-IP with AMD’s AAT demo
[EP2]

GZIP Compression demo
[EP3]

Nov 16, 2021 [ NEW PRODUCT RELEASE ]

NVMeTCP IP is the standalone host side NVMe Over Fabric (NVMe/TCP) controller with no CPU and external memory required. Enabling very high-performance remote access to NVMe-oF Storage Server by simple user logic.
Learn more : NVMeTCP IP for AMD│Learn more : NVMeTCP IP for Altera (Intel)

Nov 15, 2021

Design Gateway joins Altera (Intel) FPGA Technology Day 2021 as Platinum partner.

IFTD21 Global Dec 6-9, 2021 Read more
IFTD21 Japan Dec 7-10, 2021 Read more

Sep 1, 2021

An article about NVMeG4 IP core with PCIe Gen4 Soft IP and TOE100G IP is published on Digikey Article Library. Describes NVMe-IP implementation example and advantage on AMD KCU116 board.

AMD KCU116: The Cost-Effective 100 Gbps Network & Storage FPGA Development Platform

Aug 31, 2021 [ NEW PRODUCT RELEASE ]

UDP100G IP is now available for Altera (Intel) and AMD FPGAs.
Learn more about UDP100G IP (for AMD)┃Learn more about UDP100G IP (for Altera (Intel))

Aug 18, 2021 [ NEW PRODUCT RELEASE ]

UDP25G IP is now available for Altera (Intel) and AMD FPGAs.
Learn more about UDP25G IP (for AMD)┃Learn more about UDP25G IP (for Altera (Intel))

Jul 20, 2021

The article about TOE100G-IP and NVMeG4-IP is published on AMD Community Forums. Read the article

Jul 1, 2021

Design Gateway is AMD VAR Partner.
AMD FPGA Accelerator Cards

May 10, 2021

Design Gateway is Altera (Intel) Titanium Partner.

May 1, 2021

DG IP cores support the Altera (Intel) high-end FPGA Agilex series, TOE100G-IP is now released.
Learn more about TOE100G IP (for Altera (Intel))

LL Networking IP : UDP10GRx-IP and TOE10GLL-IP support Altera (Intel) Devices!
Learn more about TOE100G IP (for Altera (Intel))

Feb 25, 2021 [ NEW PRODUCT RELEASE ]

TOE100G IP TCP Offloading Engine IP core is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE100G-IP built by pure hardwired logic can take place of such extra CPU for TCP protocol management. This IP product includes reference design. It helps you to reduce development time and cost.
Learn more about TOE100G IP (for AMD)┃Learn more about TOE100G IP (for Altera (Intel))

Dec 7, 2020

Design Gateway joined Altera (Intel) FPGA Technology Day 2020 in Japan

Showcase

Dec 1, 2020 [ NEW PRODUCT RELEASE ]

SHA-256 IP is an optimized and efficient implementation of a secure hash algorithm SHA-256 specified in FIPS 180-4 standard. SHA256-IP can process 512-bit data blocks in just 65 clock cycles. Delivering 7.875Mbps throughput per 1MHz clock such as 1.575 Gbps throughput @ 200MHz. Learn more about SHA-256 IP

Sep 1, 2020 [ NEW PRODUCT RELEASE ]

raNVMe-IP (Random Access NVMe IP) is the new generation of NVMe-IP series which is intentionally optimized for random access. raNVMe-IP can achieve more than 500K IOPS for random write access on high performance NVMe SSD without CPU intervention. Ideal for the application such as Database Search Application which requires multiple access to NVMe SSD with best performance. Learn more about raNVMe-IP for AMD

Aug 5, 2020 [ NEW PRODUCT RELEASE ]

Jun 2, 2020 [ NEW PRODUCT RELEASE ]

New Application Specific IP is opened now. Design Gateway Co., Ltd. provides Application Specific IP cores (AS-IP) based on rich experience from provider of high-speed Storage and Networking IP Cores (Giga Bit IP cores). The AS-IP focus applications which require high-speed and low latency such as finance and network equipments.
Learn More :Application Specific IP page

Low Latency Networking IP is designed from the ground up for very low latency requirements. Especially, FinTech applications such as high-frequency trading (HFT), high speed trading (HST), Market Data Processing and Tick-to-Trade (T2T) systems. We can provide total solutions for low latency Networking IP cores and FPGA logic customization for application specific requirements. Learn more about LL Networking IP

tCAM-IP is a high performance, extremely low latency and highly configurable ternary content-addressable memory IP. tCAM-IP can make deterministic search at 200MSPS continuously speed with constant latency at 7 clock cycles. It can achieve matching/filtering performance at 2,000,000 packets per second over 40G/100G Ethernet. It is ideal for variant applications such as network packet filtering/forwarding, intelligent switch/router, deep packet inspection and network security application. Learn more about tCAM IP

May 12, 2020 [ Article RELEASE ]

An article about NVMeG3 IP core with PCIe Gen3 Soft IP is published on Digikey Article Library. Describes NVMe-IP implementation example and advantage on AMD ZCU102 board.
Read Article : Enabling the NVMe SSD Interface on a AMD ZCU102 Evaluation Kit

May 5, 2020 [ NEW PRODUCT RELEASE ]

NVMeG3IP core <for Altera (Intel)> including PCIe Gen3 Soft IP inside is released. Enabling NVMe PCIe Gen3 SSD storage solutions with no CPU/OS required. Break the barriers of NVMe SSD interface, Allow to build multi-channel RAID system with very high performance and lowest possible FPGA resources consumption.
Learn More : NVMeG3-IP core Altera (Intel) page
Introduction & Demo Video : Watch the performance demo on YouTube

Feb 5, 2020 [ NEW PRODUCT RELEASE ]

NVMeG4 IP core including PCIe Gen4 Soft IP inside is highly integrated, standalone NVMe Host Controller with built-in PCIe Gen4 root complex IP core for AMD’s high end UltraScale+ device. Enabling NVMe PCIe Gen4 SSD storage solutions with no CPU/OS required. Achieving 200% performance improvement with just +30% FPGA resources usage. Break the barriers of NVMe SSD interface, Allow to build multi-channel RAID system with very high performance and lowest possible FPGA resources consumption.
Learn More : NVMe-IP core AMD page

The result of performance of NVMeG4-IP on AMD VCU118 Write=4,288MB/sec Read=4670MB/sec.
Watch the performance demo on YouTube

Jul 10, 2019 [ NEW PRODUCT RELEASE ]

DG 10GbE MAC core implements the MAC layer for TOE/UDP10G-IP core. It is fully compatible with Altera (Intel) MAC core and highly compatible with AMD MAC. It achieves Super Low latency and High-speed networking system.

Altera (Intel)

DG 10GbE MAC core Datasheet

DG 10GbE MAC core Presentation

AMD

DG 10GbE MAC core Datasheet

DG 10GbE MAC core Presentation

Jul 1, 2019

IPL-CHP1.8V which can drive with 1.8V is just released. It directly supports 1.8V I/O of the latest FPGAs. Because it also supports both voltage of 1.8V / 2.5V / 3.3V, the design flexibility is improved.
Learn More IPLock FPGA logic security system

May 29, 2019

NVMe-IP PCI Express switch feature is just released for Altera (Intel) and AMD FPGA devices. Able to connect multi-SSDs and/or access from other host device. (About PCIe switch option, please contact us).

Evaluation Demo video on YouTube!!

Altera (Intel)

Arria® 10 GX Demo

NVMe-IP core for Altera (Intel)

AMD

KCU105 Demo

NVMe-IP core for AMD

May 13, 2019

TOE40G-IP core is the pure hardware logic solution, TCP/IP protocol is handled 100% by IP core. Enabling TCP network communication to FPGA system without need CPU/OS or external memory. The performance of TOE40G-IP core reach to nearly 5GB/s on Arria® 10 GX and Zynq Ultrascale+(ZCU102/ZCU106).

Evaluation Demo video on YouTube!!

Altera (Intel)

Arria® 10 GX Demo

TOE40G-IP core for Altera (Intel)

AMD

ZCU102/ZCU106 Demo

TOE40G-IP core for AMD

Apr 2, 2019

TOE10G-IP core supports Altera (Intel) Programmable Acceleration Card (PAC) now.
TOE10G-IP Altera (Intel) PAC Demo on YouTube
Learn More TOE10G-IP core page for Altera (Intel)

Altera (Intel) PAC
Demo on YouTube

Nov 12, 2018

DesignGateway will arrange 2nd Digital Design with FPGA Camp (DD-Camp) at Chulalongkorn University in Thailand on 20 December 2018 - 4 January 2019. DesignGateway inspire and encourage Thai’s Engineering Students to come into the field of Programmable Digital Design.

DD-Camp Facebook page

Oct 1, 2018

TOE40G-IP core is released now.
Learn More TOE40G-IP core page for AMD

Sep 21, 2018

Design Gateway joins Altera (Intel) FPGA Technology Day 2018 in Tokyo as Altera (Intel) DSN Platinum partner. We shown demonstrations of NVMe-IP on Altera (Intel) Arria® 10 SX SoC board. Learn more

NVMe-IP introduction Video Clip

Sep 6, 2018

NVMe-IP core on Altera (Intel) FPGA Inside Edge in September 2018.

Sep 6, 2018

We are pleased to partner with AXIOS / Uniquest on IP core demo at Altera (Intel) FPGA Technology Day (IFTD) 2018, Seoul, Korea.

Aug 20, 2018

Design Gateway joins Altera (Intel) FPGA Technology Day 2018 in Shenzhen as Altera (Intel) DSN Platinum partner. We will show demonstrations of NVMe-IP and TOE10G-IP on Altera (Intel) Arria® 10 SX SoC board. Learn more

Date: 17 Sep 2018 (Mon)
Place: The Westin Shenzhen Nanshan, Shenzhen, China

July 17, 2018

NVMe IP core New additional features are released.

Automatic 512/4K sector LBA support
SMART, FLUSH, Shutdown command support

Learn More NVMe-IP for Altera (Intel) / NVMe-IP for AMD
Presentation NVMe-IP for Altera (Intel) / NVMe-IP for AMD

Altera (Intel) Arria 10 SX
demo on YouTube

AMD KCU105
demo on YouTube

July 11, 2018

NVMe IP and TOE10G IP introduction and performance demo videos are available on Altera (Intel) FPGA YouTube channel.

June 14, 2018

DesignGateway provides high-speed Storage and Networking solutions and available on Altera (Intel) Arria 10 SX development kit. Evaluation demo videos are on youtube.

Learn More DesignGateway GIGA Bit IP cores for Altera (Intel)

June 6, 2018

Total solution for NVMe IP core on Altera (Intel) FPGA and Altera (Intel) optane 900p SSD. Impressive performance over 2,200MB/sec (sequential write) and over 2,700MB/sec (sequential read) on Altera (Intel) Arria 10 SoC development kit.

Learn More NVMe-IP core (Altera (Intel))
About Altera (Intel) Optane SSD 900P

NVMe-IP Demo
with Optane SSD 900P
on Arria 10 SX

Apr 27, 2018

Design Gateway is AMD Alliance Program Certified Partner. go to Alliance Program Page

Apr 1, 2018

Design Gateway is Altera (Intel) ® FPGA Design Solutions Network (DSN) Platinum Partner. go to DSN Page

Mar 2, 2018

Design Gateway NVMe-IP solutions now support PLDA PCIe Soft IP for AMD device. Enabling the unique high performance and cost-effective NVMe Host Controller solution for FPGA data storage application, especially, NVMe PCIe Gen3 support for the low-cost & high performance device family such as Kintex-7 and Zynq UltraScale+ device without embedded PCIe Gen3 Hard IP.
Watch NVMe-IP + PLDA PCIe IP Evaluation demo on youtube

Learn More NVMe-IP core (AMD)

about PLDA
about PCIe Gen3 soft IP "XpressRICH3 IP"

NVMe-IP
+
PLDA PCIe IP Demo

Feb 6, 2018

SATA IP core supports Zynq Ultrascale+.
Watch SATA IP 4ch RAID Evaluation demo on AMD Zynq Ultrascale＋(ZCU102) on youtube

Learn More SATA-IP core (AMD)

SATA-IP 4ch RAID Demo
(ZCU102)

Jan 11, 2018

SDLink is a high speed FPGA configuration module which stores data on microSD card. High availability,High capacity and High-speed programming.

Learn more about SDLink
Purchase from

Dec 20, 2017

DesignGateway arranged 1st Digital Design with FPGA Camp (DD-Camp) at Chulalongkorn University in Thailand on 14-27 December 2017. DesignGateway inspire and encourage Thai’s Engineering Students to come into the field of Programmable Digital Design.

DD-Camp Facebook page

Dec 12, 2017

DesignGateway release SATA-IP core reference design for ReFLEX CES Alaric Instant-DevKit. You can evaluate the performance of SATA-IP 4ch RAID demo and with the board now!
Learn more SATA-IP page
About ReFLEX CES

About Alaric Instant-DevKit

SATA-IP Demo
(Alaric Instant DevKit)

Dec 7, 2017

NVMe IP core supports Zynq Ultrascale+ with PCI express Gen3.
Watch NVMe IP Evaluation demo on AMD Zynq Ultrascale＋(ZCU106) on youtube

Learn More NVMe-IP core (AMD)

NVMe-IP Demo
(ZCU106)

Nov 6, 2017

DesignGateway release NVMe-IP core reference design for ReFLEX CES Alaric Instant-DevKit. You can evaluate the performance of both 1ch NVMe-IP demo and 2ch RAID0 demo with the board now!
Learn more NVMe-IP page
About ReFLEX CES / About Alaric Instant-DevKit

Sep 20, 2017

Design Gateway joins Altera (Intel) FPGA Technology Day 2017 in Tokyo as Altera (Intel) DSN Gold partner. We will show demonstrations of NVMe-IP, SATA-IP and TOE10G-IP on Altera (Intel) Arria® 10 SX SoC board.
Learn more IFTD17 page

Sep 5, 2017

Design Gateway joins Altera (Intel) FPGA Technology Day 2017 in Seoul as Altera (Intel) DSN Gold partner. We will show demonstrations of NVMe-IP, SATA-IP and TOE10G-IP on Altera (Intel) Arria® 10 SX SoC board.

Date: 12 Sep 2017 (Tue) 10:00 - 16:30
Place: Lotte Hotel World(Jamsil) 3F Emerald room, Seoul, South Korea

Jul 4, 2017

Mouser Electronics, Inc. the leading company of electronics components begins handling Design Gateway products. You can purchase SDLink high-speed configuration module, IPLock IP security system and AB Series adapter boards for IP core evaluation. Learn More: MOUSER Page

Jun 1, 2017

NVMe IP core is epochally improved to support BRAM operation without external memory such as DDR.The performance of the latest version drastically improves with built-in optimized PCIe bridge. It achieves over 3300MB/s (read) and over 2100MB/s (Write) ultra high-speed transfer on Arria® 10 SX and Kintex Ultrascale(KCU105).

Evaluation Demo video on Youtube!!

Altera (Intel)

Arria® 10 SX Demo

NVMe-IP core for Altera (Intel)

AMD

KCU105 Demo

NVMe-IP core for AMD

May 5, 2017

AB07-USB3FMC-1.8VIF for USB3.0-IP core evaluation is released. It is for Virtex-7 and VC707 board which uses 1.8V I/O.
Learn more USB3.0-IP FMC demo board Manual

Mar 1, 2017

UDP1G-IP core is released. It is ideal for network applications that require broadcast and low latency!!
UDP1G-IP core page for AMD│UDP1G-IP core page for Altera (Intel)

2016年11月1日

Design Gateway joins Altera (Intel) SoC FPGA Developper Forum (ISDF) in Tokyo as Altera (Intel) DSN Gold partner. We shown demonstrations of NVMe-IP, SATA-IP and TOE10G-IP on Altera (Intel) Arria® 10 SX SoC board.

NVMe-IP core
on Arria® 10 SX

Aug 25, 2016

Design Gateway joins Altera (Intel) FPGA Technology Day (IFTD16) in Singapore.

NVMe-IP core
on Arria® 10 SX

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