DesignGateway Hot! News February 2020

- N E W R E L E A S E - NVMeG4 IP including PCIe Gen4 Soft IP inside
NVMeG4 IP including PCIe Gen4 Soft IP inside is highly integrated, standalone NVMe Host Controller with built-in PCIe Gen4 root complex IP core for Xilinx’s high end UltraScale+ device. Enabling NVMe PCIe Gen4 SSD storage solutions with no CPU/OS required. Achieving 200% performance improvement with just +30% FPGA resources usage. Break the barriers of NVMe SSD interface, Allow to build multi-channel RAID system with very high performance and lowest possible FPGA resources consumption. (Intel version coming soon)
Learn more about NVMeG4 IP for Xilinx	Learn more about NVMe IP for Intel
Presentation (Xilinx)	Presentation (Intel)

Merits of NVMeG4 IP with PCIe Gen4 Soft IP Leveraging UltraScale+ transceiver, Enabling NVMe PCIe Gen4 SSD support for non-PCIe Gen4 Hard IP Devices Enabling Virtex UltraScale+ (VCU118) to connect and access NVMe PCIe Gen4 SSD(s) with 2X performance over single NVMe PCIe Gen3 SSD. Ideally ultra high speed storage with compact form factor systems. Small Resource Consumption Dedicatedly designed and optimized for Standalone NVMe PCIe Gen4 Host Controller. The resource consumption increase just only 30% while achieving 200% performance increase over PCIe Gen3 systems. Multi-channel NVMe RAID System NVMe IP with PCIe Soft IP does not have the limitation depend on the number of PCIe Hard IPs built in the FPGA device. It is possible to build multi-channel RAID system which maximize the number of transceivers available on FPGA device.

News NVMeG4-IP achieves 4,670MB/sec speed!! The result of performance of NVMeG4-IP including PCIe Gen4 Soft IP inside on Xilinx VCU118 Write=4,288MB/sec Read=4670MB/sec. Learn more about NVMe-IP for Xilinx The performance demo is available on YouTube. Watch here. Technical Updates NVMeG4-IP / NVMe-IP Xilinx NVMeG4 IP with PCIe Gen4 Soft IP Datasheet Rev1.0 - New NVMeG4 IP with PCIe Gen4 Soft IP Reference Design Document Rev1.0 - New NVMeG4 IP with PCIe Gen4 Soft IP Demo Instruction Document Rev1.0 - New NVMe IP Datasheet Rev3.4 - Updated NVMe IP Reference Design Document Rev3.3 - Updated NVMe IP Demo Instruction Document Rev3.3 - Updated NVMe IP by AB17 Demo Instruction Document Rev1.1 - Updated NVMeG4-IP / NVMe-IP Presentation Rev2.1 - Updated UDP1G-IP Intel UDP1G IP Demo Instruction Document Rev1.2 - Updated Events World Smart Energy Week 2020 Date: Feb 26-28, 2020 Venue: Tokyo Big Sight, Japan More Information Logis-Tech Tokyo 2020 Date: Feb 19-21, 2020 Venue: Tokyo Big Sight, Japan More Information 31st Manufacturing World Japan Date: Feb 26-28, 2020 Venue: Makuhari Messe, Japan More Information MWC 2020 Date: Feb 24-27, 2020 Venue: Fira Gran Via Av. Joan Carles I 64 08908 L’Hospitalet de Llobregat Barcelona, Spain More Information Privacy Protection Policy DesignGateway recognizes the importance of personal information protection, and strive to protect personal information. We absolutely do not transfer it to a third party. Distributed stop / Address change / Register If you do not wish us to send or if your E-mail address is changed, please contact following page. https://dgway.com/mailmaga_E.html Publisher DesignGateway Co., Ltd. http://www.design-gateway.com/ Mail：ip-sales@design-gateway.com | About Us| Contact| (c) 2020 Design Gateway Co., Ltd.