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NVMe IP corePCIeSSD can directy connect to FPGA!!

NVMe-IP

NVMe IP core is standalone NVMe Host Controller with built-in optimized PCIe Bridge and Internal Memory Buffer, designed to handle NVMe Protocol without need CPU/OS and External DDR memory. It’s recommended for the application which requires high performance, high storage capacity, very compact system size and easily to support multiple NVMe SSDs.
NVMeG3 IP including PCIe Gen3 Soft IP inside enable the NVMe SSD interface for non-embedded PCIe Gen3 Hard IP Devices. Break the barriers of NVMe interface, Allow to build multi-channel RAID system with very high performance and lowest possible FPGA resources consumption. Learn more about NVMeG3 IP
This IP core license includes the reference design for Intel® FPGA boards. It helps you to reduce development time and cost.


Features

  • Implement application layer to access NVMe PCIe SSD without CPU and external memory (DDR)
  • Simple user interface by dgIF typeS
  • Direct connect to Avalon-ST Hard IP for PCI Express from Intel by using 128-bit bus interface
  • Include 256 Kbyte RAM to be data buffer
  • Support 6 commands, i.e. IDENTIFY, WRITE, READ, Shutdown, SMART, and Flush
  • Support NVMe device
    • Base Class Code 01h (mass storage), Sub Class code 08h (Non-volatile), Programming Interface 02h (NVMHCI)
    • MPSMIN (Memory Page Size Minimum): 0 (4Kbyte)
    • MDTS (Maximum Data Transfer Size): 0 (no limitation) or at least 5 (128 Kbyte)
    • LBA unit: 512 byte or 4096 byte
  • NVMeG3 IP with PCIe Gen3 Soft IP for non-PCIe Gen3 Hard IP devices Learn more about NVMeG3 IP
  • raNVMe IP provides more than 500K IOPS Random write access without CPU Learn more about raNVMe IP
  • exFAT & FAT32 file system management without CPU usage (Option)
  • Support PCIe Switch (Customize support, please ask us)
  • Reference design with AB18-PCIeX16 adapter board available on Intel® FPGA boards and ReFLEX CES Alaric Instant-DevKit.
    Available on Mouser

Block diagram




Document download

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Common Documents

Document name Revision
DG IP core Brochure Rev2.6EA
NVMe-IP核 Rev2.4CA (中文)
NVMe-IP core Presentation Rev2.1AE
IP core Introduction Video
IP core Introduction

Reference design
Introduction

Technical Documents

Support Devices Arria® 10 SX, Arria® 10 GX
Arria® V GX
IP core &
Option
Datasheet Reference Design Document Demo Instruction Document Evaluation demo file
* ask password
Demo Video
NVMe-IP for Stratix® 10 GX Rev1.0 Rev1.0 Rev4.2
FPGA Board Setup Rev4.1
Stratix® 10 GX
NVMe-IP Rev3.4 Rev3.3 Rev4.2
FPGA Board Setup Rev4.1
Arria® 10 SX
Arria® 10 GX
Cyclone® 10 GX
Arria® V GX

ALARIC DevKit
Terasic TR5

Arria 10 SX Dev kit


ALARIC Instant DevKit
2ch RAID0 Rev1.1 Rev1.1 Arria 10 SX

Alaric DevKit
exFAT-IP for
NVMe-IP
Rev1.3 Rev1.2 Rev1.3 Arria 10 GX
FAT32-IP for
NVMe-IP
Rev1.0 Rev1.0 Rev1.0 Arria 10 SX
Arria 10 GX
NVMe IP for PCIe switch
*Customization Support. Please ask us.
Rev1.2 Rev1.1 Rev1.1 Arria 10 GX
with Linux Rev1.0 Rev1.0 Arria 10 SX

Accessories for evaluation

Accessories for evaluation Description
AB16-PCIeXOVR PCIe Cross Over adapter board for Intel FPGA boards
Download manual

Purchase
AB17-M2FMC M.2-FMC adapter board for NVMe-IP evaluation. Able to connect 2 NVMe SSDs. * SSD is not included.
Download manual

Purchase
AB18-PCIeX16 PCIe x16 Lanes Crossover adapter board for NVMe-IP evaluation
Download manual

Purchase

About price and licence of this IP core, please contact Design Gateway.

Performance

NVMe-IP core Evaluation is
available on Arria 10 SoC Board!
NVMe-IP core achieves ultra high-speed over 3300MB/sec for Read and over 2100MB/sec for Write!! You can evaluate the performance on Intel® FPGA boards with free download sof file before purchasing.

Demo video clip on youtube










Application example

NVMe-IP core is the best solution for applications which requires huge data transmission with high-speed.
Surveillance Camera Data Logger Video Editing System Medical Image Analysis Aerospace & Defense



Alliance Partner



Design Gateway Co., Ltd.

Head Office
3-23-17 Naka-cho, Koganei, Tokyo, JAPAN
R&D
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