As industries adopt FPGA-based edge computing for applications like AI inference, industrial automation, and real-time analytics, high-speed network connectivity becomes essential. However, managing 10GbE TCP/UDP communication on an SoC-based FPGA can be a significant burden on the embedded CPU. To maximize system performance, offloading TCP/UDP processing to hardware is a critical step.

Why Offload TCP/UDP Processing in FPGA Edge Solutions?

Many FPGA edge solutions integrate an SoC (CPU) for compute-intensive tasks such as AI processing, data aggregation, and real-time control. However, handling 10GbE networking in software consumes substantial CPU resources, limiting the overall efficiency of the system. A fully hardware-based TCP/UDP Offload Engine helps overcome these challenges by:

• Reducing CPU Load: Offloading TCP/IP and UDP/IP stacks to hardware frees up the CPU for critical edge computing tasks, such as AI inference and real-time decision-making.
• Maximizing 10GbE Bandwidth: A software-based approach struggles to fully utilize 10GbE speeds, while FPGA-based offloading ensures near-line-rate performance with minimal latency.
• Enhancing System Efficiency: Eliminates software bottlenecks, leading to predictable, stable, and high-performance data transfer in edge applications.

Features		CPU/Software Solution
CPU Usage	0% - Fully offloads TCP stack from CPU	100% - High CPU load to handle TCP stack
Performance & Reliability	99% stable transfer speed, with auto-retransmission support	50% unstable transfer speed under heavy load
FPGA Implementation	Easy integration on FPGA, no CPU/OS required	MPSoC with Linux implementation, but speed and reliability still difficult to achieve

Seamless 10GbE Integration for FPGA Edge Platforms

Design Gateway’s TOE10G-IP and UDP10G-IP cores offer optimized solutions for FPGA edge devices, enabling high-performance, low-latency 10GbE communication. These solutions are ideal for applications requiring real-time processing, low power consumption, and high-speed data transmission.

Additionally, TOE10G-IP is designed to work seamlessly with the built-in 10G EMAC Hard IP available on FPGA edge devices, eliminating the need for an external MAC. This integration not only reduces resource utilization but also lowers the total cost of ownership by minimizing additional hardware dependencies. By leveraging this built-in capability, developers can achieve a cost-effective, high-performance 10GbE solution without compromising efficiency.

Real-World Applications:

ADAS System Development: Developing ADAS requires high-speed data logging from sensors like cameras, LiDAR, and radar. AMD’s Versal Edge AI provides AI acceleration for real-time processing, but transmitting large datasets over 10GbE can overload the SoC CPU.

By integrating TOE10G-IP, ADAS R&D teams can Offload TCP processing to FPGA hardware, freeing CPU resources for Edge AI, ensure high-bandwidth, real-time data transmission over 10GbE, reduce latency and power consumption, optimizing system efficiency.

Machine Vision and AI Camera: Next-gen machine vision systems require flexible architectures to support evolving use cases. Altera’s Agilex 5 enables direct data ingest, pipelining images into custom ISP or AI processing with deterministic, low-latency compute. With support for custom image processing (filtering, 3D vision, deep learning) and varied data types (custom integer, floating point), Agilex 5 is ideal for AI-powered cameras. With Altera’s Agilex 5 and TOE10G-IP or UDP10G-IP, machine vision systems achieve superior speed, efficiency, and adaptability for AI-driven imaging. Learn more for Altera

Success Stories Across the Globe

Design Gateway’s TOE200GADV IP core for Optical Faber Communication

• Learn more for Altera | Intel Partner Showcase Page
• Learn more for AMD | AMD Adaptive Computing Partner Solutions Page