Introducing NVMe-IP on Agilex™ 5 E-Series

Design Gateway is excited to announce the release of our NVMe-IP core optimized for the Agilex™ 5 E-Series FPGA. Building upon our legacy of high-performance, CPU-less NVMe solutions, this latest integration leverages the advanced features of the Agilex 5 E-Series to deliver enhanced performance and efficiency.

Arria 10 vs. Agilex 5 E-Series: A Comparative Overview

Enhanced NVMe-IP Performance with Agilex 5 E-Series

The integration of NVMe-IP with the Agilex 5 E-Series FPGA brings significant performance improvements:

• Advanced PCIe Hard IP: The Agilex 5 E-Series features hardened PCIe Up to Gen4 Root Complex controllers, enabling higher data throughput and reduced latency.
• Improved Data Rates: Thanks to the enhanced transceiver speeds (up to 25.8 Gbps), users can experience up to a 10% performance boost in NVMe operations compared to previous generations (Arria 10).
• Optimized Resource Utilization: The NVMe-IP core requires less than 3000 ALMs and utilizes only 256KB of on-chip memory, eliminating the need for external DDR memory.

Demonstration on Agilex 5 E-Series Evaluation Board

We have developed a comprehensive demo showcasing the capabilities of the NVMe-IP core on the Sulfur Agliex 5 FPGA board. About Macnica Sulfur Development Kit for Agilex 5 FPGA E-Series

• NVMe IP Demo on Sulfur Agilex 5 FPGA Board

• Learn more for Altera | Intel Partner Showcase Page
• Learn more for AMD | AMD Adaptive Computing Partner Solutions Page

Our General Manager, Thanaporn Sangpaithoon, will be participating as a moderator at the "Agentic AI: What It Is and How It Will Affect the Manufacturing Industry" event on May 14. Outline