Introducing Network Offload Engine IP Cores on Altera® Agilex™ 5 E-Series

Design Gateway is proud to introduce our high-performance TOE10G-IP and UDP10G-IP cores optimized for the Altera Agilex™ 5 E-Series FPGA. As data traffic and networking demands continue to grow, our TCP/IP and UDP/IP offload engines provide hardware-based acceleration to eliminate CPU bottlenecks and maximize throughput for high-speed network applications.

By fully offloading TCP and UDP protocol processing into FPGA hardware, these IP cores enable developers to build efficient, low-latency, and high-throughput network systems ideal for financial trading, storage networking, real-time data streaming, and other bandwidth-intensive use cases.

Arria 10 vs. Agilex 5 E-Series: A Comparative Overview

Enhancing TOE10G-IP and UDP10G-IP Performance with Agilex 5 E-Series

The integration of TOE10G-IP and UDP10G-IP with the Agilex 5 E-Series FPGA provides significant advantages for high-speed networking solutions:

• Full Protocol Offload: Complete TCP (TOE10G-IP) and UDP (UDP10G-IP) processing fully handled by hardware, eliminating the need for host CPU intervention.
• Built-in EMAC Hard IP Support: Leverages Agilex 5’s embedded EMAC Hard IP, reducing resource usage and eliminating the need for EMAC Soft IP cores.
• Higher Speed Capability: Supports up to 25GbE operation, delivering faster data rates compared to previous Arria 10-based designs.
• Ready-to-Use Reference Design: Complete and verified reference designs are available on the Agilex 5 Development Board for rapid evaluation and integration.

Most modern CPUs hit a throughput bottleneck when forced to process both application logic and communication protocols at 10 Gbps. With TCP/IP or UDP/IP stacks consuming excessive resources, the effective data transfer rate often drops below 30% of theoretical bandwidth - leaving performance on the table.

Demonstration on Agilex 5 E-Series Evaluation Board

We have developed a comprehensive demo showcasing the high-speed network offload capabilities of TOE10G-IP and UDP10G-IP cores on the Macnica Sulfur Agliex 5 FPGA Development Kit. This demonstration highlights:

• Ultra-low latency hardware-based TCP and UDP processing
• Seamless high-speed Ethernet data transfer with minimal CPU usage
• Efficient resource utilization leveraging Agilex 5 built-in hard IP features

Discover how the new Agilex 5 Sulfur FPGA from Altera, paired with Design Gateway’s TOE/UDP IP, achieves full 10Gbps bandwidth with lower CPU load and power consumption.

In high-speed fields like AI, cloud computing, and 8K video, traditional CPU-based TCP/UDP handling causes bottlenecks. Our solution eliminates that.

• Video: UDP10G IP Demo on Sulfur Agilex 5 FPGA Board

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