DesignGateway Hot! News September 2019

NVMe IP with PCIe Gen3 Soft IP
NVMe IP with PCIe Gen3 Soft IP enable the NVMe SSD interface for non-embedded PCIe Hard IP Devices such as Zynq UltraScale+ (ZCU102). Break the barriers of NVMe interface, Allow to build multi-channel RAID system with very high performance and lowest possible FPGA resources consumption.
Learn more about NVMe IP for Xilinx	Learn more about NVMe IP for Intel
Presentation (Xilinx)	Presentation (Intel)

Merits of NVMe IP with PCIe Gen3 Soft IP NVMe SSDs can be driven by Cost competitive & non-PCIe Gen3 Hard IP Devices Enabling Zynq UltraScale+ (ZCU102) to connect and control NVMe SSD(s). It is very suitable for SoC based system which required very high speed storage such as video recording, processing and playback system. Small Resource Consumption Dedicatedly designed and optimized for NVMe-IP. The resource consumption is reduced by approximately 50% compared with others general purpose PCIe Gen3 Root Complex mode IP. Multi-channel NVMe RAID System NVMe IP with PCIe Soft IP does not have the limitation depend on the number of PCIe Hard IPs built in the FPGA device. It is possible to build multi-channel RAID system which maximize the number of transceivers available on FPGA device.

News NVMe-IP 4ch RAID achieves 12.6GB/sec!! The result of performance of NVMe-IP 4ch RAID on Xilinx VCU118 Write=8,119MB/sec, Read=12,857MB/sec (with SAMSUNG960 2pcs and SAMSUNG970 2pcs) Learn more about NVMe-IP for Xilinx Technical Updates NVMe-IP Xilinx NVMe IP with PCIe Gen3 Soft IP Datasheet Rev1.0 - New NVMe IP with PCIe Gen3 Soft IP Reference Design Document Rev1.0 - New NVMe IP with PCIe Gen3 Soft IP Demo Instruction Document Rev1.0 - New TOE10G-IP Intel TOE10G-IP Datasheet Rev1.3 - Updated TOE10G-IP Reference Design Document Rev1.3 - Updated TOE10G-IP CPU Demo Instruction Document Rev1.5 - Updated DG EMAC IP Loopback Reference Design Document Rev1.0 - New DG EMAC IP Loopback Demo Instruction Document Rev1.0 - New Xilinx TOE10G-IP Datasheet Rev1.9 - Updated TOE10G-IP Reference Design Document Rev1.2 - Updated TOE10G-IP CPU Demo Instruction Document Rev1.3 - Updated UDP10G-IP Intel DG EMAC IP Loopback Reference Design Document Rev1.0 - New DG EMAC IP Loopback Demo Instruction Document Rev1.0 - New Events AUTO-ID & COMMUNICATION EXPO Date: Sep 11-13, 2019 Venue: Tokyo Big Sight, Japan More Information SENSOR EXPO JAPAN 2019 Date: Sep 11-13, 2019 Venue: Tokyo Big Sight, Japan More Information Measuring Technology Expo 2019 Date: Sep 11-13, 2019 Venue: Tokyo Big Sight, Japan More Information IBC 2019 Date: Sep 13-17, 2019 Venue: RAI AMSTERDAM More Information SEMICON Taiwan 2019 Date: Sep 18-20, 2019 Venue: Taipei Nangang Exhibition Center,Taipei, Taiwan More Information Taiwan Innotech Expo 2019 Date: Sep 26-28, 2019 Venue: TWTC Exhibition Hall 1 Taipei, Taiwan More Information Industrial Automation Show Date: Sep 17-21, 2019 Venue: National Exhibition and Convention Center (NECC) Shanghai More Information electronica India Date: Sep 25-27, 2019 Venue: India Expo Centre, Greater Noida, India More Information Privacy Protection Policy DesignGateway recognizes the importance of personal information protection, and strive to protect personal information. We absolutely do not transfer it to a third party. Distributed stop / Address change / Register If you do not wish us to send or if your E-mail address is changed, please contact following page. https://dgway.com/mailmaga_E.html Publisher DesignGateway Co., Ltd. https://dgway.com/ Mail：ip-sales@design-gateway.com | About Us| Contact| (c) 2019 Design Gateway Co., Ltd.