TCP Offloading Engine IP core (TOE100G/40G/25G/10G/1G-IP) is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU
is required. TOE100G-IP built by pure hardwired logic can take place of
such extra CPU for TCP protocol management. This IP product includes reference
design for Intel FPGAs. It helps you to reduce development time.
DesignGateway provide demo file for Intel FPGA boards. You can evaluate
TOE-IP on real board before purchasing.
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![]() TOE-100G-IP |
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![]() TOE40G-IP * Click to show more detail |
![]() TOE25G-IP * Click to show more detail |
![]() TOE10G-IP * Click to show more detail |
![]() TOE1G-IP * Click to show more detail |
Document Name | Update (Revision) |
DG IP cores Brochure | Rev2.8EA |
TOE-IP core series Presentation | Rev2.0AE |
10GEMAC-IP for TOE10G-IP Presentation | Rev1.0AE |
Introduction Video ![]() |
![]() TOE25G-IP Introduction |
Blogs ![]() |
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Devices | Agilex™ 7 F-Series, Stratix®10 MX/TX | |||||
IP core & Option | Datasheet | Reference Design Document | Demo Instruction | FPGA Board Set up Document | Free Evaluation file Get Password | ![]() |
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Rev2.0 | Rev2.1 | Rev1.2 | Rev3.2 | Agilex-F Stratix 10 MX Stratix 10 TX |
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4 Session demo | Rev1.0 | Rev1.0 | Rev3.2 | Stratix 10 TX | ||
Devices | Intel PAC, Arria®10 GX | |||||
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Rev1.1 | Rev1.0 | Rev1.0 | Arria 10 GX | ![]() |
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Intel PAC | Rev1.0 | Rev1.0 | Intel PAC | ![]() |
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Devices | Agilex™ 7 F-Series, Stratix®10 GX | |||||
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Rev1.3 | Rev1.2 | Rev1.3 | Rev2.2 | Agilex-F Stratix 10 GX Stratix 10 MX |
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Devices | Intel®PAC, Stratix® 10 GX, Arria® 10 SX, Arria® 10 GX, Cyclone® 10 GX | |||||
IP core & Option | Datasheet | Reference Design Document | Demo Instruction | FPGA Board Set up Document | Free Evaluation file Get Password | ![]() |
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Rev1.9 | Rev1.7 Rev1.0 (PAC) |
Rev2.2 Rev1.0 (PAC) |
Rev3.2 | Intel PAC Stratix 10 GX Stratix 10 MX Arria 10 SX Arria 10 GX Cyclone 10 GX |
![]() Intel PAC ![]() Arria 10 SX |
10G EMAC-IP | Rev1.2 | Rev1.0 | Rev1.0 | Cyclone 10 GX | ||
Multi Session | Rev1.0 | Rev1.0 | Arria 10 SX | |||
Devices | Arria® 10 SX, Cyclone® 10 GX, Arria® V GX, Cyclone® V E, Stratix® IV GX | |||||
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Rev2.11 |
Rev1.1 | Rev2.0 | Rev2.0 | Arria 10 SX Arria V GX Cyclone V E |
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2 port demo | Rev1.0 | Rev1.0 | Cyclone 10 GX | |||
FTP server demo with SATA-IP | Rev1.0 | Rev1.0 | Cyclone 10 GX | ![]() |
The TOE100G-IP core multiple sessions reference design is implemented to utilize 100G Ethernet channel effectively and maximize
TCP throughput by multiple instances of TOE100G-IP. It impro It significantly improves the performance of TCP communication dropped due to the restrictions on the PC side without any expensive enterprise grade server. |
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DG 10GbE MAC core implements the MAC layer for TOE10G-IP core and fully compatible with
Intel MAC. It has many advantages.
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DG 10GEMAC-IP | Intel 10GEMAC | |
Tx latency (clk freq.=156.25MHz) | 19.2ns (3clk) | 76.8ns (12clk) |
Rx latency (clk freq.=156.25MHz) | 44.8ns (7clk) | 83.2ns (13clk) |
ALMs | 1362 | 1617 |
Registers | 1259 | 3015 |
Block Memory | 0 | 2320 |