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TOE-IP core Series200GbE is available on Agilex™ 7 I-Series!!

FeaturesBlock diagramDocument DownloadApplications
TOE-IP

TCP Offloading Engine IP core (TOE200G/100G/40G/25G/10G/1G-IP) is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE-IP core series built by pure hardwired logic can take place of such extra CPU for TCP protocol management. This IP product includes reference design for Altera (Intel) FPGAs. It helps you to reduce development time.
DesignGateway provide demo file for Altera (Intel) FPGA boards. You can evaluate TOE-IP on real board before purchasing.

Features

  • All pure hardware TCP/IP protocol stack
  • Support IPv4 protocol
  • Support one port connection
  • Capability to handle 4 TCP sessions with the same target * TOE200GADV-IP
  • Supports Full Duplex communication
  • Support both Server and Client mode (Passive/Active open and close)
  • Support Jumbo frame
  • User data interface: Utilizes a 1024-bit Avalon stream interface * TOE200GADV-IP
  • Super low-latency DG 10G EMAC-IP for TOE10G-IP core (Option) Learn more
  • Provide free evaluation file for FPGA Development Kits (1 hour time limited)
  • Reference design is included in IP core product

Block diagram


TOE200GADV-IP



TOE100G-IP



TOE40G-IP

TOE25G-IP

TOE10G-IP

TOE1G-IP


Document & Demo file download

Technical document update information

Sales Materials

Document Name Update (Revision)
DG IP cores Brochure Rev2023Q4
TOE-IP core series Presentation Rev2.0AE
10GEMAC-IP for TOE10G-IP Presentation Rev1.0AE
Introduction Video
TOE25G-IP Introduction
Blogs -

Technical Documents & Free Evaluation file

Devices Agilex™ 7 I-Series/F-Series, Stratix®10 MX/TX
IP core & Option Datasheet Reference Design Document Demo Instruction FPGA Board Set up Document Free Evaluation file
TOE200G-IPTOE200GADV-IP Rev1.0 Rev1.0 Rev1.0 Rev1.0 Agilex™ 7
I-Series
TOE100G-IPTOE100G-IP Rev2.0 Rev2.1 Rev1.2 Rev3.2 Agilex™ 7
F-Series

Stratix 10 MX
Stratix 10 TX
4 Session demo Rev1.0 Rev1.0 Rev3.2 Stratix 10 TX
Devices Altera (Intel) PAC, Arria®10 GX
TOE40G-IPTOE40G-IP Rev1.1 Rev1.0 Rev1.0 Arria 10 GX
Altera (Intel) PAC Rev1.0 Rev1.0 Altera (Intel) PAC
Devices Agilex™ 7 F-Series, Stratix®10 GX
TOE25G-IPTOE25G-IP Rev1.3 Rev1.2 Rev1.3 Rev2.2 Agilex-F
Stratix 10 GX
Stratix 10 MX
Devices IntelPAC, Stratix® 10 GX, Arria® 10 SX, Arria® 10 GX, Cyclone® 10 GX
IP core & Option Datasheet Reference Design Document Demo Instruction FPGA Board Set up Document Free Evaluation file
TOE10G-IPTOE10G-IP Rev2.00 Rev2.00

Rev1.0 (PAC)
Rev2.04

Rev1.0 (PAC)
Rev3.2 Altera (Intel) PAC
Stratix 10 GX
Stratix 10 MX
Arria 10 SX
Arria 10 GX
Cyclone 10 GX

Arria 10 SX

Altera (Intel) PAC
10G EMAC-IP Rev1.2 Rev1.0 Rev1.0 Rev3.2 Cyclone 10 GX
2 port demo Rev1.01 Rev1.0 Rev3.2 Arria 10 GX
Multi Session Rev1.0 Rev1.0 Rev3.2 Arria 10 SX
Devices Arria® 10 SX, Cyclone® 10 GX, Arria® V GX, Cyclone® V E, Stratix® IV GX
TOE1G-IPTOE1G-IP Rev2.11
Rev1.2 Rev2.1 Rev2.0 Arria 10 SX
Arria 10 GX
Arria V GX
Cyclone V E
2 port demo Rev1.0 Rev1.0 Cyclone 10 GX
FTP server demo with SATA-IP Rev1.0 Rev1.0 Cyclone 10 GX

Muiti-Session Reference design to improve TCP communication with PC

The TOE100G-IP core multiple sessions reference design is implemented to utilize 100G Ethernet channel effectively and maximize TCP throughput by multiple instances of TOE100G-IP.
It impro It significantly improves the performance of TCP communication dropped due to the restrictions on the PC side without any expensive enterprise grade server.
TOE100G-IP Multi-Session Demo : Picture Story Blog

Super low-latency DG 10GbE MAC core for TOE10G-IP

DG 10GbE MAC core implements the MAC layer for TOE10G-IP core and fully compatible with Altera (Intel) MAC. It has many advantages.

  • Super low-latency, Tx=19.2nsec, Rx=44.8nsec.
  • Minimized resource usage, ? of Altera (Intel) MAC core.
  • Very low price, 1/5 of Altera (Intel) MAC core.

DG 10GEMAC-IP Altera (Intel) 10GEMAC
Tx latency (clk freq.=156.25MHz) 19.2ns (3clk) 76.8ns (12clk)
Rx latency (clk freq.=156.25MHz) 44.8ns (7clk) 83.2ns (13clk)
ALMs 1362 1617
Registers 1259 3015
Block Memory 0 2320

Application Examples

TOE100G-IP is the best solution for the system which has to process big data with minimum time.
  • Multi-channel HD video streaming
  • Autonomous driving development system which consist of multi channel of Camera, Lidar, Radar and sensors
  • Medical scanners such as MRI and PET scan

TOE100G-IP introduction & Application example video clip on YouTube. Watch
TOE100G-IP & Suitable applications : Picture Story Blog

TOE10G-IP Real-World Applications


Pipeline inspection system

CT Scan

Satellite Tracking System

Semiconductor Manufacturing

Ophthalmic Medical

Video equipment

Scanning sonar
(fish detection system)

Radar system

Industrial printer

Wireless communication system
Blog Article: Proven 10G TCP Offload Engine IP Core for Industrial, Medical, and Test & Measurement Applications



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