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The Expert of IP Core & Embedded

TOE-IP core SeriesAvailable on Agilex F series!!

TOE-IP

TCP Offloading Engine IP core (TOE100G/40G/25G/10G/1G-IP) is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE100G-IP built by pure hardwired logic can take place of such extra CPU for TCP protocol management. This IP product includes reference design for Intel FPGAs. It helps you to reduce development time.
DesignGateway provide demo file for Intel FPGA boards. You can evaluate TOE-IP on real board before purchasing.

Features

  • All pure hardware TCP/IP protocol stack
  • Support IPv4 protocol
  • Support one port connection (Support Multi-session by implementing multiple cores)
  • Supports Full Duplex communication
  • Support both Server and Client mode (Passive/Active open and close)
  • Support Jumbo frame
  • Simple data & control interface
  • Super low-latency DG 10G EMAC-IP for TOE10G-IP core (Option) Learn more
  • Provide free evaluation file for FPGA Development Kits (1 hour time limited)
    Register and get password
  • Reference design is included in IP core product

Block diagram


TOE-100G-IP

TOE40G-IP
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TOE25G-IP
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TOE10G-IP
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TOE1G-IP
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Document & Demo file download

Technical document update information

Sales Materials

Document Name Update (Revision)
DG IP cores Brochure Rev2.6EA
TOE-IP core series Presentation Rev2.0AE
10GEMAC-IP for TOE10G-IP Presentation Rev1.0AE
Introduction Video
TOE25G-IP Introduction
Blogs -

Technical Documents & Free Evaluation file

Devices Agilex F-Series, Stratix®10 MX
IP core & Option Datasheet Reference Design Document Demo Instruction FPGA Board Set up Document Free Evaluation file Get Password
TOE100G-IPTOE100G-IP Rev1.0 Rev1.0 Rev1.0 Rev1.0 Agilex F
Stratix 10 GX
Devices Intel PAC, Arria®10 GX
TOE40G-IPTOE40G-IP Rev1.1 Rev1.0 Rev1.0 Arria 10 GX
Intel PAC Rev1.0 Rev1.0 Intel PAC
Devices Stratix®10 GX
TOE25G-IPTOE25G-IP Rev1.1 Rev1.0 Rev1.1 Rev2.0 Stratix 10 GX
Stratix 10 MX
Devices Intel®PAC, Stratix® 10 GX, Arria® 10 SX, Arria® 10 GX, Cyclone® 10 GX
IP core & Option Datasheet Reference Design Document Demo Instruction FPGA Board Set up Document Free Evaluation file Get Password
TOE10G-IPTOE10G-IP Rev1.7 Rev1.3

Rev1.0 (PAC)
Rev2.1

Rev1.0 (PAC)
Rev3.1 Intel PAC
Stratix 10 GX
Stratix 10 MX
Arria 10 SX
Arria 10 GX

Cyclone 10 GX

Intel PAC


Arria 10 SX
10G EMAC-IP Rev1.1 Rev1.0 Rev1.0 Cyclone 10 GX
Multi Session Rev1.0 Rev1.0 Arria 10 SX
Devices Arria® 10 SX, Cyclone® 10 GX, Arria® V GX, Cyclone® V E, Stratix® IV GX
TOE1G-IPTOE1G-IP Rev2.10 Rev1.1 Rev1.2 Rev2.0 Arria 10 SX
Arria V GX
Cyclone V E
2 port demo Rev1.0 Rev1.0 Cyclone 10 GX
FTP server demo with SATA-IP Rev1.0 Rev1.0 Cyclone 10 GX

Super low-latency DG 10GbE MAC core for TOE10G-IP

DG 10GbE MAC core implements the MAC layer for TOE10G-IP core and fully compatible with Intel MAC. It has many advantages.

  • Super low-latency, Tx=19.2nsec, Rx=44.8nsec.
  • Minimized resource usage, ? of Intel MAC core.
  • Very low price, 1/5 of Intel MAC core.

DG 10GEMAC-IP Intel 10GEMAC
Tx latency (clk freq.=156.25MHz) 19.2ns (3clk) 76.8ns (12clk)
Rx latency (clk freq.=156.25MHz) 44.8ns (7clk) 83.2ns (13clk)
ALMs 1362 1617
Registers 1259 3015
Block Memory 0 2320

Performance



Application Examples

TOE100G-IP is the best solution for the system which has to process big data with minimum time.
  • Multi-channel HD video streaming
  • Autonomous driving development system which consist of multi channel of Camera, Lidar, Radar and sensors
  • Medical scanners such as MRI and PET scan




Alliance Partner



Design Gateway Co., Ltd.

Head Office
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