DesignGateway Hot! News May 2020

NVMeG3 IP: PCIe Gen3 Soft IP built-in IP core
NVMe IP with PCIe Gen3 Soft IP enable the NVMe SSD interface for non-embedded PCIe Hard IP Devices. Break the barriers of NVMe interface, Allow to build multi-channel RAID system with very high performance and lowest possible FPGA resources consumption. It is also very suitable for SoC based system which required very high speed storage such as video recording, processing and playback system.
Learn more about NVMe IP for Xilinx	Learn more about NVMe IP for Intel
Presentation for Xilinx	Presentation for Intel

Merit of NVMe IP with PCIe Gen3 Soft IP Multi-channel NVMe RAID System NVMe IP with PCIe Soft IP does not have the limitation depend on the number of PCIe Hard IPs built in the FPGA device. It is possible to build multi-channel RAID system which maximize the number of transceivers available on FPGA device.

News NVMeG4-IP utilizes UltraRAM for Ultrascale+ devices NVMeG4-IP utilizes UltraRAM memory block for data buffer instead of BlockRAM. As a result, more BlockRAM available, better performance, less power consumption and easier to meet timing constraints for your systems. NVMeG3-IP and NVMe-IP can be also customized to utilize UltraRAM memory blocks for some specific device upon request. Learn more about NVMeG4-IP for Xilinx New Videos on YouTube NVMeG4-IP Performance Demo CPU-less NVMe-IP Introduction CPU-less UDP-IP Reference Design Introduction Technical Updates NVMeG4/G3-IP / NVMe-IP Intel NVMeG3 IP Datasheet Rev1.0 - New NVMeG3 IP Reference Design Document Rev1.0 - New NVMeG3 IP Demo Instruction Document Rev1.0 - New NVMe IP Demo Instruction Document Rev3.2 - Updated NVMe IP exFAT Demo Instruction Document Rev1.3 - Updated NVMeG3-IP / NVMe-IP Presentation Rev2.0 - Updated Xilinx NVMeG4 IP Demo Instruction Document Rev1.1 - Updated NVMeG3 IP Demo Instruction Document Rev1.1 - Updated NVMeG3 IP 4ch RAID0 Demo Instruction Document Rev1.1 - Updated NVMe IP Demo Instruction Document Rev3.4 - Updated NVMe IP 4ch RAID0 Demo Instruction Document Rev1.1 - Updated NVMe IP exFAT Demo Instruction Document Rev1.4 - Updated NVMe IP PCIe Switch Demo Instruction Document Rev1.2 - Updated NVMe IP + exFAT + TOE10G Reference Design Document Rev1.0 - New NVMe IP + exFAT + TOE10G Demo Instruction Document Rev1.0 - New Super Low Latency Networking IP for Fintech Intel Presentation Rev1.0 - New Xilinx Presentation Rev1.0 - New Events NAB Show Date: May 13-14, 2020 Venue: Online More Information Privacy Protection Policy DesignGateway recognizes the importance of personal information protection, and strive to protect personal information. We absolutely do not transfer it to a third party. Distributed stop / Address change / Register If you do not wish us to send or if your E-mail address is changed, please contact following page. https://dgway.com/mailmaga_E.html Publisher DesignGateway Co., Ltd. https://dgway.com/ Mail：ip-sales@design-gateway.com | About Us| Contact| (c) 2020 Design Gateway Co., Ltd.