DesignGateway Hot! News July 2020

	IPLock to protect FPGA circuit design from illegal copy
	Very easy to use Safely lending FPGA products Only 2 I/O connection
	Learn more about IPLock
	IPLock Demo video on YouTube

1.8V I/O version for the latest & high performance FPGA devices IPL-CHP1.8V IPL-CHP1.8V driven with 1.8V directly supports 1.8V I/O of the latest FPGAs. Because it also supports both voltage of 1.8V / 2.5V / 3.3V, the design flexibility is improved. Available on Mouser [ Presentation ] Learn more about IPLock compatible with 1.8V I/O New YouTube Videos Subscribe to DG IP core YouTube channel tCAM-IP Introduction AB Series Introduction Technical Updates tCAM-IP Intel Demo Instruction Document Rev1.0 - New Low Latency UDP10GRx-IP Xilinx Datasheet Rev1.0 - New Reference Design Document Rev1.0 - New Demo Instruction Document Rev1.0 - New NVMe-IP Xilinx Datasheet Rev3.5 - Updated Demo Instruction Document Rev4.0 - Updated NVMe-IP demo FPGA board Setup Rev4.0 - New 2ch RAID0 Reference Design Document Rev1.2 - Updated 2ch RAID0 Demo Instruction Document Rev2.0 - Updated 2ch RAID0 demo FPGA board Setup Rev2.0 - New TOE1G-IP Intel 2 port Demo Reference Design Document Rev1.0 - New 2 port Demo Instruction Document Rev1.0 - New Events The 3rd Industrial Automation & Robo-Tech EXPO Date: Jul 29-30, 2020 Place: INTEX Osaka, Japan More information SEMICON West 2020 Date: Jul 20-23, 2020 Place: * Virtual Event More information Privacy Protection Policy DesignGateway recognizes the importance of personal information protection, and strive to protect personal information. We absolutely do not transfer it to a third party. Distributed stop / Address change / Register If you do not wish us to send or if your E-mail address is changed, please contact following page. https://dgway.com/mailmaga_E.html Publisher DesignGateway Co., Ltd. http://www.design-gateway.com/ Contact Us | About Us| Contact| (c) 2020 Design Gateway Co., Ltd.