DesignGateway Hot! News
April 2018
[ TOE10G IP core ] Zero load for CPU, Loss-less transmission both Tx/Rx and full duplex!!
10GbE TCP Off-loading Engine(TOE10G-IP) IP core is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE1G/10G-IP built by pure hard-wired logic can take place of such extra CPU for TCP protocol management. This IP product includes reference design which helps you to reduce development time. DesignGateway provide demo binary file for Xilinx/Intel FPGA boards. You can evaluate TOE1G/10G-IP core on real board before purchasing.

Learn More for Xilinx
Learn More for Intel
Xilinx KC705 Demo on Youtube Intel Arria 10 SX, 2 FPGAs Demo
on Youtube
New features of TOE10G IP core
Arria 10 SX, between 2 FPGA boards Demo on youtube Achieve Ultra high performance 1238MB/sec between 2 FPGA boards!!
The result of full duplex transmission between 2 FPGA boards is achieved 1238MB/sec both direction!! High Efficiency throughput both Tx and Rx. Full Duplex transmission does not drop performance!! *evaluated on 2 Arria 10 SX FPGA boards.

TOE40G IP is coming soon!!
TOE IP core series (1G/10G) which have accumulated achievements and high evaluations from many customers will lineup more high-speed "TOE40G-IP" in Q3 year 2018. Please ask DesignGateway about more detail.

TOE10G IP Presentation for Xilinx TOE10G IP for Intel

Technical Updates
Gigabit IP cores



Date: Apr 18-20, 2018
Place: Makuhari Messe
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Date: Apr 18-20, 2018
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Place: Shanghai World EXPO Exhibition & Convention Center, China
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