TCP Offloading Engine IP core (TOE100G/40G/25G/10G/1G-IP) is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU
is required. TOE100G-IP built by pure hardwired logic can take place of
such extra CPU for TCP protocol management. This IP product includes reference
design for Xilinx FPGA. It helps you to reduce development time.
DesignGateway provide free demo file for Xilinx FPGA boards. You can evaluate
TOE-IP on real board before purchasing.
|
|
![]() TOE-100G-IP |
|||
![]() TOE40G-IP * Click to show more detail |
![]() TOE25G-IP * Click to show more detail |
![]() TOE10G-IP * Click to show more detail |
![]() TOE1G-IP * Click to show more detail |
Document name | Update (Revision) |
DG IP cores Brochure | Rev2.6EX |
TOE-IP core series Presentation | Rev2.0XE |
10G25GEMAC-IP for TOE25G/10G-IP Presentation | Rev1.0 |
IP core | ![]() |
![]() |
25GEMAC/PCS+RS-FEC IP | 10G25GEMAC-IP |
Introduction Video ![]() |
![]() |
![]() |
![]() ![]() |
![]() |
Blogs ![]() |
Applications that can be realized with TOE100G-IP | |||
Digikey Article Library | Digikey Article Library: Xilinx KCU116: The Cost-Effective 100 Gbps Network & Storage FPGA Development Platform |
Devices | Alvero U250, Vertex UltraScale+ VCK190, Kintex UltraScale+ KCU116 | |||||
IP core & Option | Datasheet | Reference Design Document | Demo Instruction Document | FPGA Board Setup | Free Evaluation demo file ask password | ![]() |
![]() |
Rev1.2 | Rev1.2 | Rev1.1 | Rev3.3 | VCK190 U250 KCU116 Silicom KU15P |
![]() |
4 Session demo | Rev1.0 | Rev1.0 | Rev3.1 | KCU116 | ![]() |
|
2 Port demo | Rev1.0 | Rev1.0 | Rev3.1 | |||
DMA on Alveo card |
Rev1.0 | Rev1.0 | Rev1.0 | U250 U50 |
![]() |
|
Silicom NIC card | Rev1.0 | Rev1.0 | Rev1.0 | Silicom fb2CGhh@KU15P |
![]() |
|
Devices | Kintex Ultrascale KCU105, Zynq Ultrascale+ ZCU102 / ZCU106 | |||||
![]() |
Rev1.2 | Rev1.0 | Rev1.2 | - | KCU105 ZCU102 ZCU106 |
![]() |
Devices | Virtex UltraScale+ VCU118, Kintex UltraScale+ KCU116 |
|||||
![]() |
Rev1.5 | Rev1.4 | Rev1.2 | Rev2.5 | VCK190 VCU118 KCU116 |
|
25GEMAC/PCS +RS-FEC IP |
Rev1.0 | Rev1.0 | Rev1.0 | KCU116 | ![]() |
|
10G25G EMAC-IP | Rev1.3 | ![]() |
||||
4 Session demo | Rev1.0 | Rev1.0 | Rev2.4 | VCK190 | ||
2 Port demo | Rev1.0 | Rev1.0 | Rev2.4 | |||
FTP Server demo with NVMe-IP & exFAT-IP | Rev1.0 | Rev1.0 | Rev1.0 | KCU116 | ||
Devices | Zynq UltraScale+ ZCU106/ZCU102, Virtex UltraScale+ VCU118 Kintex UltraScale KCU105 |
|||||
IP core & Option | Datasheet | Reference Design Document | Demo Instruction Document | FPGA Board Setup | Free Evaluation demo file ask password | ![]() |
![]() |
Rev1.14 | Rev1.4 | Rev2.1 | Rev3.3 | ZCU106 ZCU102 VCU118 KCU105 ZC706 |
|
VC707/KC705 | Half DuplexRev1.0 Full DuplexRev1.0 |
Half DuplexRev1.2 Full DuplexRev1.1 |
VC707 KC705 |
![]() |
||
10G25G EMAC-IP | Rev1.3 | ![]() |
||||
FTP Server demo with NVMe-IP & exFAT-IP | Rev1.2 | Rev2.0 | Rev2.1 | ZCU102 ZCU106 KCU105 |
||
Multi Session | Rev1.0 | Rev1.0 | ZC706 KC705 VC707 |
|||
Devices | Zynq-7000 ZC706, Virtex-7 VC707, Kintex-7 KC705, Artix-7 AC701 | |||||
![]() |
Rev2.10 | Rev1.1 | Rev2.0 | Rev3.0 | KC705 AC701 |
![]() |
Multi Session | Rev1.0 | Rev1.0 | KC705 | |||
2 port demo | Rev1.3 | Rev1.2 | ZC706 KC705 AC701 |
|||
FTP server demo with SATA-IP | Rev1.1 | Rev1.1 | ZC706 KC705 |
![]() |
The TOE100G-IP core multiple sessions reference design is implemented to utilize 100G Ethernet channel effectively and maximize
TCP throughput by multiple instances of TOE100G-IP. It impro It significantly improves the performance of TCP communication dropped due to the restrictions on the PC side without any expensive enterprise grade server. |
![]() |
A 100G data transfer using TCP between a Linux host's memory and a 100G Ethernet connection can be achieved by utilizing the TOE100G-IP along with Silicom's PacketMover framework on their fb2CG@KU15P Kintex UltraScale+ FPGA Card. | ![]() |
The 25G EMAC/PCS + RS-FEC IP core provides a comprehensive implementation of the physical layer, including
the Ethernet MAC layer, Physical Coding sublayer (PCS), and RS-FEC sublayer.
The incorporation of RS-FEC in the system significantly enhances data reliability
and connection stability, making it an ideal option for applications that
prioritize data reliability. The demo is ready available for IP core evaluation. This demo aims to provide a simple yet comprehensive demonstration of the capabilities of The 25G EMAC/PCS + RS-FEC IP, connected to the Xilinx Transceiver, which enables the physical and medium of the 25G Ethernet system. |
|
![]() |
KEY FEATURES
|
![]() |
Loopback Demo is available on KCU116
The demo is ready available for IP core evaluation. This demo aims to provide a simple yet comprehensive demonstration of the capabilities of The 25G EMAC/PCS + RS-FEC IP, connected to the Xilinx Transceiver, which enables the physical and medium of the 25G Ethernet system. The round-trip latency time is 471.04 ns. (packet size 9014 bytes) |
DG 10G25GEMAC core implements the MAC layer for TOE10G-IP core and highly compatible with
Xilinx MAC. It has many advantages.
|
![]() |
DG 10G25GEMAC-IP | Xilinx 10GEMAC | |
Tx latency (clk freq.=156.25MHz) | 19.2ns (3clk) | 19.2ns (3clk) |
Rx latency (clk freq.=156.25MHz) | 44.8ns (7clk) | 115.2ns (18clk) |
CLB LUTs | 1873 | 3498 |
CLB Registers | 1072 | 3291 |
CLB | 326 | 694 |