DesignGateway Co., Ltd. The Expert of IP Core [TOE-IP core series]

TOE-IP core SeriesSupport 200GbE, Multi-session & AXI4 interface

Features | Block diagram | Document Download | Applications | 25GEMAC/PCS + RS-FEC IP

TCP Offloading Engine IP core (TOE200G/100G/40G/25G/10G/1G-IP) is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE-IP core series built by pure hardwired logic can take place of such extra CPU for TCP protocol management. This IP product includes reference design for AMD FPGA. It helps you to reduce development time.
DesignGateway provide free demo file for AMD FPGA boards. You can evaluate TOE-IP on real board before purchasing.

Features

All pure hardware TCP/IP protocol stack
Support IPv4 protocol
Support one port connection
Support Multi-session * TOE200G/100GADV-IP
Supports Full Duplex communication
Support both Server and Client mode (Passive/Active open and close)
Support Jumbo frame

Simple data & control interface, support AXI4-ST interface * TOE200G/100GADV-IP
AXI4 stream interface with AMD Ethernet MAC
Super low-latency DG 10G EMAC-IP for TOE10G-IP core (Option) Learn more
Provide free evaluation bit file for FPGA Development Kits (1 hour time limited)
Reference design is included in IP core product

Block diagram

TOE200GADV-IP			TOE100GADV-IP
TOE100G-IP	TOE40G-IP	TOE25G-IP	TOE10G-IP	TOE1G-IP

Document & Demo bit file download

Technical document update information

Sales Materials

Document name	Update (Revision)
DG IP cores Brochure	Rev2.6EX
TOE-IP core series Presentation	Rev2.0XE
10G25GEMAC-IP for TOE25G/10G-IP Presentation	Rev1.0

YouTube & Blogs

IP core		25GEMAC/PCS+RS-FEC IP	10G25GEMAC-IP
Introduction Video
Blogs	Applications that can be realized with TOE100G-IP
Digikey Article Library	AMD KCU116: The Cost-Effective 100 Gbps Network & Storage FPGA Development Platform Accelerate AI Applications on Xilinx VCK190 Evaluation Kit with Design Gateway's IP Cores Evaluation Kit

Technical Documents & Free Evaluation file

Devices	Alvero U250, Versal AI Core VCK190, Kintex UltraScale+ KCU116
IP core & Option	Datasheet	Reference Design Document	Demo Instruction Document	FPGA Board Setup	Free Evaluation demo file
TOE200GADV-IP			Rev1.0
TOE100GADV-IP	Rev1.0	Rev1.0	Rev1.0	Rev3.3	VCK190 KCU116
TOE100G-IP	Rev2.0	Rev2.0	Rev1.2	Rev3.3	VCK190 U250 KCU116 Silicom KU15P
exFAT2-IP FTP Server Demo			Rev1.00	Rev1.00	VCK190
4 Session demo		Rev1.1	Rev1.0	Rev3.3	KCU116
2 Port demo		Rev1.1	Rev1.0	Rev3.3
DMA on Alveo card		Rev1.0	Rev1.0	Rev1.0	U250 U50
Silicom NIC card		Rev1.0	Rev1.0	Rev1.0	Silicom fb2CGhh@KU15P
Devices	Zynq Ultrascale+ ZCU102 / ZCU106, Kintex Ultrascale KCU105
TOE40G-IP	Rev1.2	Rev1.0	Rev1.2	-	KCU105 ZCU102 ZCU106
Devices	Versal AI Core VCK190 Zynq Ultrascale+ ZCU111, Virtex UltraScale+ VCU118, Kintex UltraScale+ KCU116
TOE25G-IP	Rev1.5	Rev1.4	Rev1.3	Rev2.5	VCK190 VCU118 KCU116 ZCU111
25GEMAC/PCS +RS-FEC IP	Rev1.0	Rev1.0	Rev1.0		KCU116
10G25G EMAC-IP	Rev1.3
4 Session demo		Rev1.0	Rev1.0	Rev2.5	VCK190
2 Port demo		Rev1.0	Rev1.0	Rev2.5
FTP Server demo with NVMe-IP & exFAT-IP		Rev1.0	Rev1.0	Rev1.0	KCU116
Devices	Versal AI Core VCK190 Zynq UltraScale+ ZCU106/ZCU102, Virtex UltraScale+ VCU118, Kintex UltraScale KCU105
IP core & Option	Datasheet	Reference Design Document	Demo Instruction Document	FPGA Board Setup	Free Evaluation demo file
TOE10G-IP	Rev2.01	Rev2.00	Rev2.04	Rev3.04	VCK190 ZCU106 ZCU102 VCU118 KCU116 KCU105 ZC706
		VC707/KC705 Half Duplex Rev1.01 Full DuplexRev1.0	VC707/KC705 Half Duplex Rev1.03 Full DuplexRev1.1		VC707 KC705
10G25G EMAC-IP	Rev1.3
2 port demo		Rev1.00	Rev1.0	Rev3.04	KCU105
FTP Server demo with NVMe-IP & exFAT-IP		Rev1.2	Rev2.0	Rev2.1	ZCU102 ZCU106 KCU105
Multi Session		Rev1.0	Rev1.0		ZC706 KC705 VC707
Devices	Zynq-7000 ZC706, Virtex-7 VC707, Kintex-7 KC705, Artix-7 AC701
TOE1G-IP	Rev2.12	Rev1.2	Rev2.1	Rev3.0	KC705 AC701
Multi Session		Rev1.0	Rev1.0		KC705
2 port demo		Rev1.4	Rev1.3		KC105 ZC706 KC705 AC701
FTP server demo		Rev1.1	Rev1.1		ZC706 KC705

Performance

TOE100G-IP achieves 12GB/sec with AMD KCU116 and Alveo U250. The performance demo on Youtube

Watch YouTube

TOE100G-IP Performance Demo : Picture Story Blog

Muiti-Session Demo

The TOE100G-IP core multiple sessions reference design is implemented to utilize 100G Ethernet channel effectively and maximize TCP throughput by multiple instances of TOE100G-IP.
It impro It significantly improves the performance of TCP communication dropped due to the restrictions on the PC side without any expensive enterprise grade server.

TOE100G-IP Multi-Session Demo : Picture Story Blog

PacketMover Performance Demo

A 100G data transfer using TCP between a Linux host's memory and a 100G Ethernet connection can be achieved by utilizing the TOE100G-IP along with Silicom's PacketMover framework on their fb2CG@KU15P Kintex UltraScale+ FPGA Card.

Blog Article: TOE100G-IP with Silicom’s PacketMover Performance Demo on fb2CG@KU15P FPGA Card

25GEMAC/PCS+RS-FEC IP

The 25G EMAC/PCS + RS-FEC IP core provides a comprehensive implementation of the physical layer, including the Ethernet MAC layer, Physical Coding sublayer (PCS), and RS-FEC sublayer. The incorporation of RS-FEC in the system significantly enhances data reliability and connection stability, making it an ideal option for applications that prioritize data reliability. The demo is ready available for IP core evaluation. This demo aims to provide a simple yet comprehensive demonstration of the capabilities of The 25G EMAC/PCS + RS-FEC IP, connected to the AMD Transceiver, which enables the physical and medium of the 25G Ethernet system.
	KEY FEATURES 25Gbps Ethernet MAC + PCS with RS-FEC 64bit XGMII interface @ 390.625MHz AXI4-stream for connecting with user logic & DG’s Network IP: TOE25G-IP & UDP25G-IP Support mode: Transmit packet length: 1 ? 9014 bytes with zero-padding capability Frame check sequence insertion detection and marking for received frames Frame check sequence error detection and marking for received frames Customization features upon request Leading low resource usage & low latency
	Loopback Demo is available on KCU116 The demo is ready available for IP core evaluation. This demo aims to provide a simple yet comprehensive demonstration of the capabilities of The 25G EMAC/PCS + RS-FEC IP, connected to the AMD Transceiver, which enables the physical and medium of the 25G Ethernet system. The round-trip latency time is 471.04 ns. (packet size 9014 bytes)

25GEMAC/PCS+RS-FEC IP YouTube Videos
[part1] Enhancing Data Reliability in 25G Ethernet Systems with Reed Solomon Forward Error Correction	[part2] 25G Ethernet MAC IP Suite: 10G25G EMAC IP vs 25G EMAC/PCS + RS-FEC IP	[part3] Ultra-Low Latency 25GEMAC/PCS + RS-FEC IP Demo on AMD KCU116
Read Blog Article	Read Blog Article	Read Blog Article

Super low-latency DG 10G25G EMAC IP core

DG 10G25GEMAC core implements the MAC layer for TOE10G-IP core and highly compatible with AMD MAC. It has many advantages.

Super low-latency, Tx=19.2nsec, Rx=44.8nsec.
Minimized resource usage, 1/2 of AMD MAC core.
Very low price, 1/5 of AMD MAC core.

	DG 10G25GEMAC-IP	AMD 10GEMAC
Tx latency (clk freq.=156.25MHz)	19.2ns (3clk)	19.2ns (3clk)
Rx latency (clk freq.=156.25MHz)	44.8ns (7clk)	115.2ns (18clk)
CLB LUTs	1873	3498
CLB Registers	1072	3291
CLB	326	694

Application Examples

TOE100G-IP is the best solution for the system which has to process big data with minimum time.

Multi-channel HD video streaming
Autonomous driving development system which consist of multi channel of Camera, Lidar, Radar and sensors
Medical scanners such as MRI and PET scan

TOE100G-IP introduction & Application example video clip on YouTube. Watch
TOE100G-IP & Suitable applications : Picture Story Blog

TOE10G-IP Real-World Applications

Pipeline inspection system		CT Scan
Satellite Tracking System	Semiconductor Manufacturing	Ophthalmic Medical	Video equipment
Scanning sonar (fish detection system)	Radar system	Industrial printer	Wireless communication system

Blog Article: Proven 10G TCP Offload Engine IP Core for Industrial, Medical, and Test & Measurement Applications

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