DesignGateway Hot! News September 2018

[ SATA IP ] Scalably Enhance more Speed & Storage capacity with RAID0 Reference Design!!
SATA IP core is high-reliability and high performance for many customers and has rich options for various user applications. One of advantage of SATA IP core is able to scalably to enhance transmission speed and storage capacity of your system with RAID0 reference design. Host controller IP (HCTL-IP) all pure hardware logic realizes the best performance with RAID system. We can provide the best solution for your SATA application. For more detail: SATA-IP Related Products Selection Guide
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RAID System for Xilinx	RAID System for Intel

SATA IP core - Suitable solution for RAID system High-Efficiency Loss less RAID system The intelligent RAID controller specifically designed for SATA IP core realizes loss less RAID system. it is scalable expansion of storage capacity & speed. Small Resource Usage Resource consumption of single SATA IP core is very small, so it effects to saving total resource of multi-channels. RAID0 free Reference Design 4ch (or 8ch) RAID0 reference design for Xilinx/Intel FPGA boards are free provided with IP core license. User can confirm core operation with original reference design, and then modify a little to approach final user product. It provides no risk to back to re-build and able to develop for short term. Adapter boards for RAID development Design Gateway provides FMC-10ch SATA adapter board(AB09-FMCRAID) and HSMC-8ch SATA adapter board for IP core performance evaluation on Xilinx/Intel FPGA boards. These are also useful for RAID system development after IP core purchasing. These adapter boards are available on Mouser.

News Design Gateway joins Intel FPGA Technology Day 2018 Design Gateway joins Intel FPGA Technology Day 2018 in Seoul, Shenzhen and Tokyo. We will show IP core demonstrations on Arria 10 SX SoC board. Sep 6, 2018 in Seoul * Uniquest Booth Sep 17, 2018 in Shenzhen Sep 21, 2018 in Tokyo Technical Updates UDP1G-IP Intel UDP1G IP Datasheet Rev1.2 - Updated UDP1G IP Reference Design Document Rev1.1 - Updated UDP1G IP Demo Instruction Document Rev1.1 - Updated TOE10G-IP Xilinx TOE1G IP Datasheet Rev2.7 - Updated Events Intel FPGA Technology Day 2018 Shenzhen Date: Sep 17, 2018 Place: The Westin Shenzhen Nanshan, Shenzhen, China More Information Design Gateway joins the exhibition. Intel FPGA Technology Day 2018 TOKYO Date: Sep 21, 2018 Place: Hotel Gajoen Tokyo More Information Design Gateway joins the exhibition. 20th AUTO-ID & COMMUNICATION EXPO Date: Sep 12-14, 2018 Place: Tokyo Big Sight, Japan More Information SENSOR EXPO JAPAN 2018 Date: Sep 26-28, 2018 Place: Tokyo Big Sight, Japan More Information Electronica India Date: Sep 26-28, 2018 Place: BIEC Bengaluru, India More Information Privacy Protection Policy DesignGateway recognizes the importance of personal information protection, and strive to protect personal information. We absolutely do not transfer it to a third party. Distributed stop / Address change / Register If you do not wish us to send or if your E-mail address is changed, please contact following page. https://dgway.com/mailmaga_E.html Publisher DesignGateway Co., Ltd. http://www.design-gateway.com/ Mail：ip-sales@design-gateway.com | About Us| Contact| (c) 2018 Design Gateway Co., Ltd.