DesignGateway Hot! News August 2019

[ DESIGN GATEWAY NETWORKING IP CORES ] Super Low Latency demo: Loopback 1883 times in 1 msec!
TOE/UDP-IP core series is the epochal solution implemented without CPU. It achieves Super Low latency and High-speed networking system with optimized DG EMAC IP core.
TOE40G-IP	TOE10G-IP	UDP10G-IP
TOE40G-IP for Xilinx TOE40G-IP for Intel	TOE10G-IP for Xilinx TOE10G-IP for Intel * DG EMAC IP available	UDP10G-IP for Xilinx UDP10G-IP for Intel * DG EMAC IP available

New Topics of DG Networking IP cores Super Low Latency, Loopback 1883 times in 1 msec UDP10G-IP core loopback demo with DG EMAC IP core achieves super low latency. [Performance Result] Total time of 8 bytes data looped back 1 million times ＝531m sec. * include data transmission time and PHY latency. UDP10G-IP + DG EMAC IP loopback performance demo will be available soon. UDP10G-IP + DG EMAC IP loopback Reference Design Document for Intel TOE40G-IP supports Intel PAC!! TOE40G-IP core is available for Intel Programmable Acceleration Card (PAC). The performance evaluation demo is on YouTube. Watch the demo on YouTube Learn more about TOE40G-IP for Intel

Technical Updates UDP10G-IP / DG EMAC-IP Intel UDP10G IP loopback Reference Design Document Rev1.0 - New Events NEPCON ASIA 2019 Date: Aug 28-30, 2019 Venue: Shenzhen Convention and Exhibition Center, China More Information 2019 SET EXPO Date: Aug 26-29, 2019 Venue: Expo Center Norte Red Pavilion & Convention Center, Sao Paulo Brazil More Information Privacy Protection Policy DesignGateway recognizes the importance of personal information protection, and strive to protect personal information. We absolutely do not transfer it to a third party. Distributed stop / Address change / Register If you do not wish us to send or if your E-mail address is changed, please contact following page. https://dgway.com/mailmaga_E.html Publisher DesignGateway Co., Ltd. https://dgway.com/ Mail：ip-sales@design-gateway.com | About Us| Contact| (c) 2019 Design Gateway Co., Ltd.