
	View on Web Design Gateway Hot! News April 2021 (1)

Design Gateway tCAM IP is a high performance, extremely low latency and highly configurable ternary content-addressable memory IP. tCAM-IP can make deterministic search at 200MSPS continuously speed with constant latency at 7 clock cycles. It can achieve matching/filtering performance at 200,000,000 packets per second over 40G/100G Ethernet. We can provide tCAM-IP custom reference design together with TOE40G/10G/1G-IP, UDP40G/10G/1G-IP and EMAC-IP based on customer requirements. Contact Us Read 1 minute instant blog : Introduction of tCAM Read 1 minute instant blog : 7 clock!! super low latency search demo on real FPGA board
Learn more about Super Low Latency tCAM IP
Features Key width 64/56/48/40/32/24/16 bits Up to 1M rule entries Searching latency is constant at 7 clock cycles Up to 200 MSPS @ 200MHz searching speed, 1,000,000 Search/MHz Easy to customize rule table memory Simple rule table memory setup and user interface signals Free evaluation demo combined with DG TOE1G-IP core is available	Target Application Network packet filtering/forwarding Intelligent switch/router Deep Packet Inspection (DPI) Big data filtering Performance Demo on FPGA board
	tCAM-IP performance demo

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What is Latency?
Why does Latency matter?

Latency and fast response is becoming more important factor for industries such as FinTech or Financial technology and remote operation or Telesurgery. Design Gateway’s Low Latency Networking IP is designed from the ground up for very low latency requirements. We can provide total solutions for low latency Networking IP cores and FPGA logic customization for application specific requirements. For more detail please visit LL Networking IP page

Technical Updates

The latest Technical Documents Update

NVMe-IP
- Datasheet (Common)
- Reference Design Document(Xilinx)
- 2ch RAID0 Reference Design Document & Demo Instruction (Xilinx)
- DDR Reference Design Document & Demo Instruction (Xilinx)
TOE25G-IP Datasheet, FPGA setup document (Intel)
TOE10G-IP Datasheet, FPGA setup document (Intel)
UDP1G-IP Datasheet (Intel)
LL Networking IP Datasheet,Reference Design Document, FPGA setup document, Demo Instruction (Intel)
tCAM-IP Datasheet, Reference Design Document (Intel)

Events

5th AI EXPO TOKYO [Spring] Outline
1st QUANTUM COMPUTING EXPO TOKYO [Spring] Outline
Date : April 7-9, 2021, Venue : Tokyo Big Sight, Japan

Meditec Japan
Date : April 14-16, 2021, Venue : Tokyo Big Sight, Japan Outline

1st XR EXPO TOKYO - VR/AR/MR -
Date : April 14-16, 2021, Venue : Tokyo Big Sight, Japan Outline

Interop Tokyo 2021 Outline
Date : April 14-16, 2021, Venue : Makuhari Messe & Streaming
Date : April 19-23, 2021, Venue : Online

HANNOVER MESSE
Date : April 12-16, 2021 Outline

DesignCon 2021
Date : April 16-18, 2021, Venue : San Jose McEnery Convention Center San Jose, CA Outline

NEPCON China 2021
Date : April 21-23, 2021, Venue : Shanghai World Expo Exhibition & Convention Centre Outline