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[ NEW RELEASE ] NVMeTCP-IP : End-To-End NVMe-OF TCP Connectivity With No CPU!

NVMeTCP IP is the standalone host side NVMe Over Fabric (NVMe/TCP) controller with no CPU and external memory required. Enabling very high-performance remote access to NVMe-oF Storage Server by simple user logic. Greatly reduce design complexity and development time. Allowing your FPGA Card/Board to get access to the existing NVMe-oF storage infrastructure remotely and directly over FPGA’s network interface with maximum possible performance. Read more about NVMeTCP IP for Xilinx * Please ask about NVMeTCP IP for Intel

Merits & Advantages of NVMeTCP IP core

Simply attach the remote NVMe SSD Storage to your FPGA Card/Board without PCIe hard IP and/or MPSoC Very high performance with over 95% network bandwidth utilization. Enabling NVMeoF(NVMe/TCP) host side on your FPGA with no CPU and DDR Scalable storage capacity & performance with multiple IPs implementation

Applications

Event driven data recording to remote storage

Distributed data retrieval and analytics systems

The event driven data recorder actively sends recorded data from the local side when the recording conditions are met. In the case of a centralized management type surveillance camera, image transfer from the camera always occurs, wasting network bandwidth, but The PUSH data recorder significantly reduces network bandwidth consumption. Since NVMeTCP-IP does not require Linux and expensive high-performance ARM processor, the system startup time is very short, small-scale and low-cost FPGAs are available, reducing power consumption by standby mode and saving network bandwidth.

After storing data from sensors and cameras, Data analytics systems require reading recorded data from remote storage and performing data analysis on multiple different hosts in parallel. Analysis systems using NVMeTCP-IP core free Host CPU resources from NVMe / TCP protocol processing and allow CPU resources to be concentrated on complex analysis tasks, dramatically improving analysis efficiency and performance.

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