The Expert of IP Core & Embedded

NVMeTCP IP is the standalone host side NVMe Over Fabric (NVMe/TCP) controller with no CPU and external memory required. Enabling very high-performance remote access to NVMe-oF Storage Server by simple user logic. Greatly reduce design complexity and development time. Allowing your FPGA Card/Board to get access to the existing NVMe-oF storage infrastructure remotely and directly over FPGA’s network interface with maximum possible performance.
This IP core license includes the reference design for Xilinx FPGA boards. It helps you to reduce development time and cost.

Features

• NVMe/TCP (NVMe over TCP) host controller (Initiator), based on NVMe-oF specification rev 1.1 and NVMe specification rev 1.4
• Access one NVMe SSD on the target (Subsystem), selected by NVMe name (NQN)
• Command: Write and Read
• High performance:
  • NVMeTCP25G-IP: Write = 2500MB/s, Read = 2600MB/s (1MB buffer)
  • NVMeTCP10G-IP: Write = 1200MB/s, Read = 1200MB/s (1MB buffer)
• Data interface: Memory-mapped interface
• Data size per command: Fixed at 4 Kbytes
• Maximum command: 256 or less, limited by Read buffer size for Read command
• Configurable Read buffer size: 32Kbytes (up to 8 Read Cmd) - 1Mbytes (up to 256 Read Cmd)
• Supported NVMe/TCP target:
  • IOCCSZ (I/O Queue Command Capsule Support Size): More than or equal to 4160 (1040h)
  • MQES (Maximum Queue Entries Supported): More than or equal to 256 (100h)
  • MAXCMD (Maximum Outstanding Commands): More than or equal to 256 (100h)
  • Authentication: Not required
• Networking: 10Gb Ethernet speed in the same network for transferring ARP request/reply packet by using jumbo frame packet
• Ethernet MAC interface: 64-bit AXI4 Stream interface at 156.25 MHz
• User clock frequency: 156.25 MHz, the same clock as EMAC interface
• Available reference design: KCU105/ZCU102/ZCU106 board
• Customized service
  • NVMe/TCP Target in different network that cannot transfer ARP packet to get Target MAC address
  • The network that does not support jumbo frame packet

Block diagram

Performance Comparison

Document download

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Technical document update page

Common Documents

Document name	Update (Revision)
Brochure
Presentation
Blog Article
YouTube Video	NVMeTCP-IP Introduction	NVMeTCP-IP performance Demo

Documents for each Device families

Support Devices	Zynq UltraScale+ ZCU102, ZCU106, Kintex UltraScale KCU105
IP core & Option	Datasheet	Reference Design Document	Demo Instruction Document	FPGA Board Set up Document	Free Evaluation demo file ask password
NVMeTCP25G-IP	Rev1.1	Rev1.0	Rev1.0	Rev1.0	KCU116 SilicomKU15P
NVMeTCP10G-IP	Rev1.1	Rev1.1	Rev1.1	Rev1.1	KCU105 ZCU106 ZCU102

Free Bit file for evaluation

Free evaluation demo is available on Xilinx FPGA boards.

Merits & Advantages of NVMeTCP IP core

• Simply attach the remote NVMe SSD Storage to your FPGA Card/Board without PCIe hard IP and/or MPSoC
• Very high performance with over 95% network bandwidth utilization.
• Enabling NVMeoF(NVMe/TCP) host side on your FPGA with no CPU and DDR
• Scalable storage capacity & performance with multiple IPs implementation

Application example

Event driven data recording to remote storage The event driven data recorder actively sends recorded data from the local side when the recording conditions are met. In the case of a centralized management type surveillance camera, image transfer from the camera always occurs, wasting network bandwidth, but The PUSH data recorder significantly reduces network bandwidth consumption. Since NVMeTCP-IP does not require Linux and expensive high-performance ARM processor, the system startup time is very short, small-scale and low-cost FPGAs are available, reducing power consumption by standby mode and saving network bandwidth

Distributed data retrieval and analytics systems After storing data from sensors and cameras, Data analytics systems require reading recorded data from remote storage and performing data analysis on multiple different hosts in parallel. Analysis systems using NVMeTCP-IP core free Host CPU resources from NVMe / TCP protocol processing and allow CPU resources to be concentrated on complex analysis tasks, dramatically improving analysis efficiency and performance

About price and licence of this IP core, please contact Design Gateway.

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