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May 2022 (2)
CPU-less Ultra Low Latency Security IP cores
[SHA256-IP & AES128/256-IP ]


Achieves high-Security with the Minimum clock cycle on FPGA




SHA256-IP can process 512 bit data blocks in just 65 clock cycles. Delivering 7.875Mbps throughput per 1MHz clock such as 2.362 Gbps throughput @ 300MHz. *tentative

Learn more about SHA256-IP

AES128 IP is designed to support ECB mode for both encryption and decryption. AES128-IP computes 128-bit data blocks within constant 11 clock cycles. (AES-256 IP :15 clock cycles)

Learn more about AES128/256-IP


SHA256-IP Introduction Video

AES128-IP Introduction Video

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DG LL UDP10GRx-IP 16 Sessions Demo

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