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FPGA Value added Solutions
Design Gateway's products that enable flexible upgrades and enhanced security for FPGA products. Available to purchase from Mouser with a short delivery time.
SDLink FPGA Configuration Module	IPLock FPGA Logic Security System
SDLink a high speed FPGA configuration module which stores configuration data on microSD card is able to be mixed/switch use with Intel/Xilinx configuration ROMs. By adopting SDLink first, product development and early product release will be possible without waiting for the standard ROM to be obtained.	IPLock is FPGA logic security system which used very reliable AES encryption technology. IP properties in FPGA are protected from illegal copy by only including IP Lock in FPGA and connecting with encryption controller chip.
Read more about SDLink SDLink Demo on YouTube Purchase SDLink from Mouser	Read more about IPLock IPLock Demo on YouTube Purchase IPLock from Mouser
Mixed use with Std. ROMs PCB design guide Schematic check support Please contact us	IPL-CHP1.8V supports both voltage of 1.8V / 2.5V / 3.3V, the design flexibility is improved.

Easy to update the circuit by swapping microSD!!

	[For Developers] More easy to Evaluate various circuit patterns!
	If you prepare multiple microSD cards and program deferent configuration data, you can evaluate and test these circuit patterns without suspending to re-program. Your development will be drastically faster!! More detail
No Need Programming tools No Need Download Cable No Need System suspended	[For Product updates] More quickly to mass-product updates!
	Just to swap microSD card to update the circuit data immediately. Because you do not need to program to board directly anymore, you can quickly support circuit modification, update and change setting after delivery. More detail

"IPLock" AES Encryption IP Security System

	Easy to protect your IP core & logic data !
	Step1: Prepare SOIC-8 pattern for security chip on your board Step2: When you need FPGA logic protection, purchase IPLock Step3: Compile your FPGA logic with IPLock core Step4: Put IPLock security chip on FPGA board Step5: Complete IP core protection! Learn more about IPLock
	Technology for Strong Protection
	AES-128 encryption Change & encrypt authentication data every 200msec cycle Generate true random authentication data by natural random number generator Immediately stop user logic when removing the chip Learn more about IPLock

YouTube Videos

Subscribe to DG IP core YouTube channel
Part1: NVMeTCP25G-IP 4 session demo Introduction	Part2: NVMeTCP25G-IP 4 session Performance demo

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