April 20, 2022
#002 Using Multiple DDR Banks
Based on Xilinx’s VitisTM Application Acceleration Development Flow Tutorial: https://github.com/Xilinx/Vitis-Tutorials/tree/2021.2/Hardware_Acceleration/Feature_Tutorials/04-mult-ddr-banks By default, the data transfer between the Kernel and the DDR is accomplished by using single DDR. In some applications, transferring large amount of data between global memory (DDR) and FPGA can be a cause of performance dropped. Using multiple DDR banks can be one of the solutions. Therefore, this...