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December 2020
[ N E W R E L E A S E ] SHA-256 IP - Super Low latency Security IP
SHA-256 IP is an optimized and efficient implementation of a secure hash algorithm SHA-256 specified in FIPS 180-4 standard. SHA256-IP can process 512-bit data blocks in just 65 clock cycles. Delivering 7.875Mbps throughput per 1MHz clock such as 1.575 Gbps throughput @ 200MHz. This IP core includes reference design. You can evaluate free demo file on real FPGA board before purchasing. Learn more about SHA-256 IP

Watch SHA-256 Introduction Video


What's SHA-256?
SHA-256 is one of the most secure and practically unbreakable hashing functions which is most popular to use in various applications such as secure password hashing, digital signature, SSL/TLS certificate and Bitcoin cryptocurrency.
"High-speed data transmission" with "Security" to be High value-added Apps
Together with Design Gateway's data storage IP and networking IP, SHA256-IP enables more opportunity for inventing the secure, efficient and high performance applications.

News
DG IP cores listed on the latest Xilinx Vivado 2020.2 !!
Design Gateway's NVMeG3-IP and CPU less SATA Host IP now listed as customize IP on IP catalog in the latest Xilinx Vivado 2020.2.
Learn more about Xilinx Vivado® Design Suite HLx edition

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SHA-256 IP Introduction

TOE10GLL IP Introduction

Technical Updates
IP core Brochure
NVMe-IP seriesTOE-IP seriesUDP-IP series
AS-IP (Low latency networking IP / tCAM-IP/ SHA-256 IP)

Events
Intel® FPGA Technology Day 2020
Date : Today - Dec 7, 2020- * Virtual event Outline
Design Gateway is co-sponsoring and exhibiting at this event.

SEMICON Japan Virtual
Date : Live - Dec 11-18, 2020 / On demand - Dec 11, 2020 - Jan 15, 2021
Outline

INTERNATIONAL TECHNICAL EXHIBITION ON IMAGE TECHNOLOGY & EQUIPMENT 2020
Date : Dec 2-4, 2020 / Venue : PACIFICO YOKOHAMA Hall D, JapanOutline

2020 International Electronics Circuit Exhibition (Shenzhen)
Date : Dec 2-4, 2020 / Venue : Halls 1, 2, 4, Shenzhen Convention & Exhibition Center, China
Outline



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