View on Web Design Gateway Hot! News February 2021 |
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Minimum 3.2ns Super Low Latency Networking IP for Fintech | |
Low Latency Networking IP for Xilinx | Low Latency Networking IP for Intel |
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Super Low Latency |
Our EMAC implements both MAC layer and PCS (Physical Coding Sublayer) to reduce latency and able to interface directly with both Xilinx and Intel 10Gb PHY IP. Our TCP an UDP Offload Engine IP is designed to handle TCP/UDP protocol stack without need CPU and optimize for super low latency and high throughput. | |
Minimum Latency 3.2 ns(Rx) / 6.4 ns(Tx) * LL UDP10G IP |
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Design for FinTech Application |
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