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Super Low Latency Networking IPfor fintech

Design Gateway’s Low Latency Networking IP is designed from the ground up for very low latency requirements. Especially, FinTech applications such as high-frequency trading (HFT), high speed trading (HST), Market Data Processing and Tick-to-Trade (T2T) systems. We can provide total solutions for low latency Networking IP cores and FPGA logic customization for application specific requirements. Contact Us

Features

Low Latency 10GEMAC-IP (LL10GEMAC-IP)

  • Super low latency for 32bit @ 312.5MHz interface
    • TX Latency: ~29ns
    • RX Latency: ~42ns
  • Compare with Intel LL 10G MAC, High-performance, Lower FPGA resource usages and Lower cost
  • Best fit for DG’s Low Latency Networking IP Cores

Low Latency UDP10G Rx/Tx-IP

  • All Hard wired Logic
  • CPU less and no external memory required
  • Support Multicast and Unicast
  • Support Multi-session up to 4 sessions (More sessions can be customized)
  • Join/Leave group by IGMPv2 protocol
  • Direct connect with super low latency DG 10GbE MAC core (LL10GEMAC-IP)
  • HDL design for minimized resource and latency
  • RX Latency: 41.6 ns (13 cycles @ 312.5 MHz)
  • TX Latency: 35.2 ns (11 cycles? @ 312.5 MHz, payload=4bytes)

Low Latency TOE10G-IP

  • All Hard wired Logic
  • CPU less and no external memory required
  • Support 1 sessions (More sessions can be customized)
  • Direct connect with super low latency DG 10GbE MAC core (LL10GEMAC-IP)
  • HDL design for minimized resource and latency
  • RX Latency: 51.2 ns (16 cycles @ 312.5 MHz)
  • TX Latency: 44.8 ns (@ 312.5 MHz, payload=4bytes)

Example FinTech Implementation on FPGA



Design Gateway Provides optimized IP & Customized service for Fintech
  • UDP10GTx / UDP10GRx, TOE10GLL, LL10GEMAC
  • Customized service

Document download

Document name Update (Revision)
Datasheet Coming soon
Presentation 1.0E
Leaflet Coming soon
For more detail, please Contact Us



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Design Gateway Co., Ltd.

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