The Expert of IP Core & Embedded

• 10 Gbps Ethernet MAC and PCS
• Directly connecting with Altera transceiver PHY (PMA) by 32-bit interface
• Low latency: 65.1 ns for round-trip latency
  18.6 ns for Tx path, 21.7 ns for Rx path,
  24.8 ns for PMA latency
• Small resource utilization
• Minimum Tx packet size: 5 bytes
• FCS (CRC-32) inserting and checking
• Individual clock domain for transmit and receive interface at 322.265625 MHz
• Reference design available on Altera FPGA board

Low Latency UDP10G Rx-IP

• All Hard wired Logic, CPU less and no external memory required
• Support Multicast and Unicast (IGMPv2)
• Support Multi-session up to 4 sessions (More sessions can be customized)
• Direct connect with super low latency DG 10GbE MAC core (LL10GEMAC-IP)
• HDL design for minimized resource and latency
• RX Latency: 3.1 ns (1 cycles @ 312.265625 MHz)
• About UDP10G Tx-IP, please ask.

Low Latency TOE10G-IP (TOE10GLL-IP)

• All Hard wired Logic, CPU less and no external memory required
• Support 1 sessions (More sessions can be customized)
• Direct connect with super low latency DG 10GbE MAC core (LL10GEMAC-IP)

• HDL design for minimized resource and latency
• RX Latency: 46.5 ns (@ 322.265625 MHz)
• TX Latency: 6.2 ns (@ 322.265625 MHz, packet size 45 bytes)