本文へスキップ

The Expert of IP Core & Embedded

┃

Super Low Latency Networking IPfor fintech

Design Gateway’s Low Latency Networking IP is designed from the ground up for very low latency requirements. Especially, FinTech applications such as high-frequency trading (HFT), high speed trading (HST), Market Data Processing and Tick-to-Trade (T2T) systems. We can provide total solutions for low latency Networking IP cores and FPGA logic customization for application specific requirements. Contact Us

Features

Low Latency 10GEMAC-IP (LL10GEMAC-IP)

  • Super low latency for 32bit @ 312.5MHz interface
    • TX Latency: ~29ns
    • RX Latency: ~42ns
  • Compare with Intel LL 10G MAC, High-performance, Lower FPGA resource usages and Lower cost
  • Best fit for DG’s Low Latency Networking IP Cores

Low Latency UDP10G Rx/Tx-IP

  • All Hard wired Logic
  • CPU less and no external memory required
  • Support Multicast and Unicast
  • Support Multi-session up to 4 sessions (More sessions can be customized)
  • Join/Leave group by IGMPv2 protocol
  • Direct connect with super low latency DG 10GbE MAC core (LL10GEMAC-IP)
  • HDL design for minimized resource and latency
  • RX Latency: 3.1 ns (1 cycles @ 312.265625 MHz)
  • TX Latency: 6.2 ns (2 cycles @ 322.265625 MHz, packet size < 45bytes)

Low Latency TOE10G-IP

  • All Hard wired Logic
  • CPU less and no external memory required
  • Support 1 sessions (More sessions can be customized)
  • Direct connect with super low latency DG 10GbE MAC core (LL10GEMAC-IP)
  • HDL design for minimized resource and latency
  • RX Latency: 46.5 ns (@ 322.265625 MHz)
  • TX Latency: 6.2 ns (@ 322.265625 MHz, packet size 45 bytes)

Example FinTech Implementation on FPGA



Design Gateway Provides optimized IP & Customized service for Fintech
  • UDP10GTx / UDP10GRx, TOE10GLL, LL10GEMAC
  • Customized service

Document download

Document name Update (Revision)
Presentation 1.0E
Brochure 2.6EA
LL 10GEMAC-IP Datasheet Rev1.0
Reference Design Document Rev1.0
FPGA board Setup Document Rev1.0
Loopback Demo Instruction Rev1.0
Evaluation demo file * (please ask password, Contact Us) Arria 10 GX
LL UDP10GRx-IP Datasheet Rev1.0
Reference Design Document Rev1.0
FPGA board Setup Document Rev1.0
Demo Instruction Rev1.1
Evaluation demo file * (please ask password, Contact Us) Arria 10 GX
TOE10GLL-IP Datasheet Rev1.1
Reference Design Document Rev1.1
Demo Instruction Rev1.0
Evaluation demo file * (please ask password, Contact Us) Arria 10 GX
For more detail, please Contact Us



Alliance Partner



Design Gateway Co., Ltd.

Head Office
3-23-17 Naka-cho, Koganei, Tokyo, JAPAN
R&D
89/13 Amornpan 205 Tower1, 11th floor, Ratchadapisek7 (Nathong) Alley, Ratchadapisek Road, Din Daeng, Bangkok, 10400 THAILAND