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Breaking Latency Barriers in Stock Trading with DG Low-Latency Network IP cores & AMD Xilinx Accelerator Card
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We are thrilled to introduce the integration of our Low-latency Network IP suites with the AMD Xilinx FPGA Accelerator Card and the Accelerated Algorithmic Trading (AAT) reference design. This resulted in solutions that could overcome the latency limitation and deploy fast adaptive trading algorithms.

DG's Low Latency Network IP Suites are designed from the ground up for very low latency requirements. They consist of TCP/UDP offload engine and EMAC cores and are targeted to be used in FinTech applications such as HFT, HST, Market Data Processing and Tick-to-Trade (T2T) systems. AMD Xilinx Accelerated Algorithmic Trading (AAT) is an open-source trading system reference design for AMD Xilinx FPGA Accelerator Card. Supports the CME market data platform and can be used to create adaptive trading algorithm and easy to deploy broad range of low latency algorithmic trading applications.
Receive Latency for Market Data	Transmit Latency for Ordering
Total Latency : 98.2 ns	Total Latency : 59.1 ns
LL10GEMAC IP 21.7 ns UDP10GRx IP 37.2 ns adapter logic for clock domain conversion 39.3 ns	adapter logic for clock domain conversion 28.1 ns TOE10GLL IP 6.2 ns MAC I/F 6.2 ns LL10GEMAC IP 18.6 ns

Low Latency Network IP cores & AAT demo YouTube Videos

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Breaking Latency Barriers in Stock Trading with AMD Xilinx AAT & DG Low Latency IP cores Read Blog Article	Design Gateway Low Latency 10G EMAC-IP with Xilinx AAT demo	Low Latency UDP10GRx-IP 16 Sessions demo for FinTech	Low Latency TOE10GLL-IP 32 Sessions Demo on ZCU106