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Design Gateway Hot! News
June 2021
Low Latency & High-Security IP core series
[AES128-IP / SHA256-IP / tCAM-IP]


Design Gateway's low latency & high throughput security IP cores is easy to connect to DG high-speed storage IPs and networking IPs. Enabling more opportunity for inventing the secure, efficient and high performance applications. Learn More

Achieves high-security with the minimum clock cycle on FPGA

N E W R E L E A S E
AES128 IP is designed to support ECB mode for both encryption and decryption. AES128-IP computes 128-bit data blocks within constant 11 clock cycles. Delivering 11.6Mbps throughput per 1MHz clock such as 2.9 Gbps throughput @ 250MHz. Learn More

SHA256 IP is an optimized and efficient implementation of a secure hash algorithm SHA-256 specified in FIPS 180-4 standard. SHA256-IP can process 512-bit data blocks in just 65 clock cycles. Delivering 7.875Mbps throughput per 1MHz clock such as 1.575 Gbps throughput @ 200MHz. Learn More

tCAM-IP is a high performance, extremely low latency and highly configurable ternary content-addressable memory IP. tCAM-IP can make deterministic search at 200MSPS continuously speed with constant latency at 7 clock cycles. It can achieve matching/filtering performance at 200,000,000 packets per second over 40G/100G Ethernet. It is ideal for variant applications such as network packet. Learn More

Example of secure system with encryption and filtering functions

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Security IP cores Overview
[tCAM-IP/SHA256-IP/AES128-IP]

AES128 IP Introduction

DG Blog: AES IP

Technical Updates
IP core Brochure
NVMe-IP seriesTOE-IP seriesUDP-IP series
AS-IP (Low latency networking IP / tCAM-IP/ SHA256-IP / AES128-IP)

Events
IMAGE SENSING SHOW 2021
Date: June 9-11, 2021 Venue : Pacifico Yokohama Outline

OPTICS PHOTONICS International Exhibition 2021
Date: June 30 - July 11, 2021 Venue : Pacifico Yokohama Outline

E3 2021
Date: June 12-15, 2021 Online Outline

Communic Asia
Date: July 14-16, 2021 Online Outline

ANGA COM DIGITAL
Date: June 8-10, 2021 Online Outline



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