Aerospace and defense (A&D) systems are pushing two extremes at once:

1. Edge capture without loss - multi-sensor payloads (radar, EW/ELINT, EO/IR, wideband RF) must be recorded continuously at high rate, while operators or mission software read the same data in real time.
2. On-board analytics at scale - AI/ML and signal processing pipelines require massive working memory and fast random access to petabyte-scale archives. Meeting these demands typically involves large external DRAM or HBM, which add significant size, weight, power, and cost overhead.

Design Gateway’s muNVMe-IP and rmNVMe-IP address these twin demands directly on FPGA, using off-the-shelf NVMe SSDs.

muNVMe-IP : Real-time capture with simultaneous Read

What it is: a compact, streaming-friendly NVMe Host controller IP optimized for deterministic, sustained recording to NVMe SSDs - with read access during recording. muNVMe-IP for AMD | muNVMe-IP for Altera

Key capabilities

• Sustained multi-channel write pipelines.
• Simultaneous read and write path for live view, extraction, or health monitoring while acquisition continues.
• Small FPGA footprint; straightforward user-logic integration for sensor/ADC/DMA streams.
• Operates independently - no CPU or external memory required, enabling fully self-contained storage pipelines.

Three wideband inputs (radar, EW, EO/IR) write concurrently to SSD while the mission computer reads a live subset for situational awareness and cueing—no dropped frames, no copy overhead.

• muNVMe-IP for AMD
• muNVMe-IP for Altera
• Contact Design Gateway

rmNVMe-IP : high-speed random access to massive datasets

What it is: NVMe Host Controller IP delivers 4KB-granularity memory access directly to your FPGA logic—perfect for real-time algorithms, AI inference, or signal processing that demand rapid, non-sequential reads across large memory spaces. rmNVMe-IP for AMD | rmNVMe-IP for Altera

Key capabilities

• Direct, low-latency random access to SSD data at 4KB page size—natural for AI/ML tiles, FFT windows, and database-like lookups.
• Simultaneous read and write path for live view, extraction, or health monitoring while acquisition continues.
• Fits on data-plane FPGAs beside your compute engines (DSP, AI, compression).
• Reduces external DRAM/HBM needs, cutting system cost, size, and power.
• Offloads storage-related tasks from the CPU, freeing up processing cycles for mission-critical workloads.

An FPGA reads sparse 4KB tiles across multi-SSD storage as “working memory” for SAR image formation, object detection, or post-mission forensics—without staging terabytes into DRAM.

• rmNVMe-IP for AMD
• rmNVMe-IP for Altera
• Contact Design Gateway