The Expert of IP Core & Embedded

rmNVMe-IP (Random Access & Multi User NVMe IP) is very high performance NVMe Host Controller which is highly optimized for high-IOPS random access applications. rmNVMe-IP supports multiple user interfaces, each user can simultaneously read/write to a single NVMe SSD at the same time. This IP is designed for the application that requires very random access performance such as real-time sensors data fusion and processing, OS file systems offloading and NVMe SSD tester. By pure hardware logic implementation, rmNVMe-IP is best in class in energy efficient, high performance and low FPGA resource usages for next generation applications.

No CPU/DDR required Standard Type	No PCIe Hard IP required	>500K IOPS random write access	Multi user simultaneously access	Random Access By Multiple Users

NVMe-IP core series Selection Guide to choose suitable solution

Introduction Videos

rmNVMe-IP : Introduction Blogs

rmNVMe-IP : Application Blogs

Features NVMe host controller for access one NVMe SSD without CPU and external memory Two user interfaces (one-Write user and one-Read user) operating simultaneously User#0 (Main user): Identify, Shutdown, Read, SMART, and Flush User#1 (Sub user): Write Support multiple Write and Read commands for 4Kbyte random access Configurable Command Depth of Write and Read command independently: 32, 64, 128, 256 Buffer size (depends on Command Depth): 128Kbyte (32 Commands) - 1Mbyte (256 Commands) Simple user interface by using data stream interface User clock frequency: More than or equal to a half of PCIe clock frequency (250 MHz for Gen4) Operating with Avalon-ST Hard IP for PCIe by using 4-lane PCIe Gen4 (128-bit bus interface) Connect to one NVMe SSD directly (without PCIe switch)

Block Diagram

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* Features and specifications are planned and subject to change without notice.

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Technical Documents

Support Devices	Agilex™ F series
IP core	Datasheet	Reference Design Document	Demo Instruction Document	Free Evaluation demo file * ask password	Demo Video
rmNVMe-IP	Coming soon, will be released in Q1 2023

Application Example

Multithreading for Database Server

The FPGA can be utilized as the offload engine for the database server to access storage, NVMe SSD. In large-scale systems, multiple threads frequently access the database, leading to a high volume of read and write requests being sent to the CPU. The write data, which is usually of a large size, is stored in the main memory. The FPGA platform's PCIe engine provides an interface that allows the offload engine to receive command requests from the CPU and directly access the data in the main memory with high performance.

The File Offload Engine sends read and write requests to the rmNVMe IP via the Read Command Interface and Write Command Interface, respectively. All write data is transferred via the Write Data Interface and stored in the NVMe SSD. The read data from the NVMe SSD is returned to the File Offload Engine via the Read Data Interface and finally, returned to the thread through the main memory.

By utilizing this hardware system, the database can be accessed with high performance while requiring less CPU resources.