The Expert of IP Core & Embedded

• NVMe host controller for access one NVMe SSD without CPU and external memory
• Support 4 users (Gen4) / 2 users (Gen3) to access one SSD simultaneously
• Simple user control I/F and FIFO interface for data port
• Include 256K bytes or 1M bytes RAMs for per user
• Command support:
  • User#0 (Main user): Identify, Shutdown, Write, Read, SMART, and Flush
  • User#1-3 (Sub user): Write and Read
• Supported NVMe device
  • Base Class Code:01h (mass storage), Sub Class Code:08h (Non-volatile), Programming Interface:02h (NVMHCI)
  • MPSMIN: 0 (4KB)
  • MDTS: At least 5 (128 KB) or 0 (no limitation)
  • LBA unit: 512 bytes or 4096 bytes
  • Support multiple queues
• User clock frequency must be more than or equal to PCIe clock (250MHz for Gen3/Gen4)
• Operating with Integrated Block for PCI Express from AMD by using 4-lane PCIe Gen3 (128-bit bus interface) or PCIe Gen4 (256-bit bus interface)
• One muNVMe IP connects to one NVMe SSD directly

• Available reference design:
  • Four-user demo on VCK190
  • Two-user demo on KCU116 and ZCU106
  • 2-ch RAID0 demo on ZCU106
• Customized service for following features
  • Additional NVMe commands
  • Increase user channel
• NVMe-IP for AMD FPGAs listed on AMD Adaptive Computing Partner Solutions

Block diagram

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• Multi-user NVMe-IP (muNVMe-IP) PCIe Gen4 IP core introduction
• 2X performance increase with RAID0x2 by muNVMe-IP core

• for Aerospace
• for Medical
• for HPC

Aerospace

Medical

HPC