The Expert of IP Core & Embedded

• NVMe host controller for access one NVMe SSD without CPU and external memory
• Support 4 users to access one SSD simultaneously (Gen4)
• Simple user control I/F and FIFO interface for data port
• High speed (1 MB RAM per user) or Small memory (256 KB RAM per user)
• Command support:
  • User#0 (Main user): Identify, Shutdown, Write, Read, SMART, and Flush
  • User#1-3 (Sub user): Write and Read
• Supported NVMe device
  • Base Class Code:01h (mass storage), Sub Class Code:08h (Non-volatile), Programming Interface:02h (NVMHCI)
  • MPSMIN: 0 (4KB)
  • MDTS: At least 5 (128 KB) or 0 (no limitation)
  • LBA unit: 512 bytes or 4096 bytes
  • Support multiple queues
• User clock frequency: More than or equal to a half of PCIe clock frequency (250 MHz for Gen4)
• PCIe Gen4 Hard IP: 128-bit interface (P-Tile/F-Tile Avalon-ST Altera FPGA for PCIe)
• One muNVMe IP connects to one NVMe SSD directly

• Available reference design:
• Customized service for following features
  • Additional NVMe commands such as Format, Write Zeroes, and Sanitize
  • Increase user channel
• Listed in the Altera Solution Acceleration Partner Offerings

Block diagram

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