Design Gateway Hot! News
September 2026
TOE & UDP IP Core now ready for Agilex 9 devices
TOE10G-IP for Altera → UDP10G-IP for Altera →

NEW DEVICE SUPPORT

TOE & UDP IP Core now proven on Agilex 9 Direct-RF

Agilex 9 solved the RF problem. The link off the board is the next challenge.

Altera’s Agilex™ 9 Direct RF-Series puts wideband data converters, logic and DSP in a single package — the reason it is showing up in adaptive radar, cognitive EW and software-defined communications. But once the converters are that wide, the bottleneck moves to how the data gets out.

RF converters to 10GbE with no CPU in the data path

AGILEX™ 9 DIRECT RF-SERIES · TOE10G-IP & UDP10G-IP

What TOE & UDP 10G IP offers

Four things worth knowing before you scroll on.

Agilex 9 Direct-RF joins the list
Both cores now sit alongside Agilex 5, Agilex 7, Arria 10 and Cyclone 10 GX support — same interface, same integration effort.
Max. 1,200 MB/s, measured
Sustained on a single 10GbE port on Agilex 9. Not a peak reading, and not dependent on what the host is doing.
Proven on Altera's DevKit
Our IP cores are validated on the DK-DEV-3ARF-FD-A DevKit, ensuring seamless and worry-free integration
Built for A&D timelines
No OS and no driver in the data path, and a scaling path to 25G, 40G and 100G when the requirement moves.

Use Case with DG's IP Core & Agilex 9

Phased-array radar
Phased-array radar and beamforming

The array produces a continuous stream and the processing cluster expects it on time. UDP10G-IP moves raw or partially processed IQ off Agilex 9 at wire speed, with the timing set by the fabric rather than by a scheduler.

• Try UDP10G-IP Demo for Agilex 9 →
SIGINT and EW capture
SIGINT and electronic warfare capture

A wideband capture is worth nothing with holes in it. TOE10G-IP does retransmission in hardware, so data reaches the recorder complete without a host TCP stack between the converter and the disk.

• Try TOE10G-IP Demo for Agilex 9 →
SATCOM ground segment and telemetry
SATCOM ground segment and telemetry

Long-lived programmes carry the cost of every layer they certify. An FPGA-only link removes the operating system and the driver from the mission path, and removes them from the qualification package with it.

• Talk to us →

Watch the Agilex 9 demo

1,200 MB/s sustained over 10GbE with the CPU out of the loop — build, run and measurement in full.

CPU-Free 10GbE TCP/UDP Offload on Altera Agilex 9 — 1,200 MB/s FPGA Demo
New Demo
CPU-Free 10GbE TCP/UDP Offload on Altera Agilex 9 — 1,200 MB/s FPGA Demo
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Request TOE & UDP IP Demo on Agilex 9
TOE-IP core series for Altera → UDP-IP core series for Altera →
TOE-IP core series for AMD → UDP-IP core series for AMD →